ADC1410S105HN-C1 - 14-bit 105Msps ADC | NXP | 40-HVQFN
部品番号: ADC1410S105HN-C1 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.2 | $252.00 |
| 100 | $22.1 | $2,210.00 |
| 500 | $19.5 | $9,750.00 |
| 1,000 | $17.8 | $17,800.00 |
ADC1410S105HN-C1 概要
An ADC (Analog-to-Digital Converter) is a data-conversion integrated circuit that samples continuous analog voltage levels and converts them into discrete digital codes at a fixed sampling rate, enabling digital signal processing, FPGA/ASIC ingest, and software analysis of real-world sensor and RF waveforms. Pipelined ADCs are a subset of the converter hierarchy (Nyquist-rate ADC -> pipelined -> successive-approximation / sigma-delta / flash) that achieve a favorable trade-off between sample rate, resolution, and power consumption, making them the default choice for communications baseband, digital oscilloscopes, and instrumentation front ends.
Key features of the ADC1410S105HN-C1 include 14-bit resolution, 105 Msps maximum sampling rate, 1-channel single-ended pipelined core, selectable CMOS or LVDS DDR digital interface for flexible FPGA/ASIC data capture, SPI-compatible serial configuration, and an exposed thermal pad enabling efficient heat removal. The 40-pin HVQFN footprint (6x6 mm) integrates supply, ground, reference, analog input, clock, and LVDS/CMOS data lanes in a compact surface-mount land pattern.
Typical applications include communications baseband receivers, medical imaging front ends, portable and benchtop test and measurement instruments (oscilloscopes, digitizers, spectrum analyzers), software-defined radio (SDR) IF sampling, and industrial data-acquisition modules. The 105 Msps rate comfortably digitizes IF frequencies in the 30-40 MHz band and supports multi-carrier LTE/3G reference designs.
When designing with this device, ensure the analog input network (transformer or driver) presents a proper 50 ohm or differential match and that the exposed pad is soldered to a sufficient copper pour for thermal relief. Decouple AVDD and DVDD separately with low-ESR ceramic capacitors placed within 2 mm of the supply pins.
ドロップイン代替品: ADC1410S105HN-C1 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC1410S105HN-C1 （同一形状・フットプリント） — 相違点: Package, Input Type, Operating Temperature, Number of Channels, Configuration Interface.
クイック比較ツール — 並列比較する代替部品を選択:
ADC1410S125HN-C1
✅ ドロップイン✓ 在庫あり
$20.95 / 個
データシートを見る →ADC1410S080HN-C1
✅ ドロップイン✓ 在庫あり
$18.75 / 個
データシートを見る →ADC1410S065HN-C1
✅ ドロップイン✓ 在庫あり
$10.75 / 個
データシートを見る →ADC1010S105HN/C1:5
✅ ドロップイン✓ 在庫あり
$9.62 / 個
データシートを見る →ADC1012D080HN/C1:5
✅ ドロップイン✓ 在庫あり
$12.1 / 個
データシートを見る →ADC1410S105HN-C1 最大定格＆電気的特性
| Number of Bits | 14 |
| サンプリングレート | 105 Msps |
| Number of Inputs | 1 |
| Input Type | Single-Ended |
| Architecture | Pipelined |
| Data Interface | CMOS or LVDS DDR |
| Configuration | S/H-ADC |
| Ratio - S/H:ADC | 1:1 |
| Number of A/D Converters | 1 |
| パッケージ | 40-HVQFN (6x6 mm, SOT618-6) with exposed pad |
| 動作温度 | -40C to +85C (Industrial) |
| Screening Level | Industrial |
| ピン数 | 40 |
| 実装タイプ | Surface Mount |
| Lead Free / RoHS | Compliant (per HVQFN SOT618-6 MO-220) |
| Control Interface | Serial SPI |
| Reference Type | Internal (per datasheet) |
| Sample Rate Family | 65 / 80 / 105 / 125 Msps variants |
ADC1410S105HN-C1 ピン構成
| ピン 1 | AVDD — Analog supply voltage (per family datasheet) |
| ピン 2 | VIN — Analog single-ended input |
| ピン 3 | AGND — Analog ground |
| ピン 4 | VCM — Common-mode voltage output |
| ピン 5 | VREF — Voltage reference decoupling |
| ピン 6 | CLK+ — Differential clock input (positive) |
| ピン 7 | CLK- — Differential clock input (negative) |
| ピン 8 | DRE — Data-ready output enable |
| ピン 9 | DVDD — Digital supply voltage |
| ピン 10 | DGND — Digital ground |
| ピン 11 | D0/D0+ — LVDS DDR data bit 0 (or CMOS bit 0) |
| ピン 12 | D0-/D1 — LVDS DDR data bit 0 negative (or CMOS bit 1) |
| ピン 13 | D1+/D2 — LVDS DDR data bit 1 positive (or CMOS bit 2) |
| ピン 14 | D1-/D3 — LVDS DDR data bit 1 negative (or CMOS bit 3) |
| ピン 15 | D2+/D4 — LVDS DDR data bit 2 positive (or CMOS bit 4) |
| ピン 16 | D2-/D5 — LVDS DDR data bit 2 negative (or CMOS bit 5) |
| ピン 17 | D3+/D6 — LVDS DDR data bit 3 positive (or CMOS bit 6) |
| ピン 18 | D3-/D7 — LVDS DDR data bit 3 negative (or CMOS bit 7) |
| ピン 19 | D4+/D8 — LVDS DDR data bit 4 positive (or CMOS bit 8) |
| ピン 20 | D4-/D9 — LVDS DDR data bit 4 negative (or CMOS bit 9) |
| ピン 21 | D5+/D10 — LVDS DDR data bit 5 positive (or CMOS bit 10) |
| ピン 22 | D5-/D11 — LVDS DDR data bit 5 negative (or CMOS bit 11) |
| ピン 23 | D6+/D12 — LVDS DDR data bit 6 positive (or CMOS bit 12) |
| ピン 24 | D6-/D13 — LVDS DDR data bit 6 negative (or CMOS bit 13) |
| ピン 25 | DCLK+ — LVDS DDR data clock positive |
| ピン 26 | DCLK- — LVDS DDR data clock negative |
| ピン 27 | OUTMODE — Output mode select (CMOS or LVDS DDR) |
| ピン 28 | CSN — SPI chip select (active low) |
| ピン 29 | SCLK — SPI serial clock |
| ピン 30 | SDIO — SPI serial data input/output |
| ピン 31 | RESET — Hardware reset (active low) |
| ピン 32 | PD — Power-down control |
| ピン 33 | OE — Output enable |
| ピン 34 | TEST1 — Test mode 1 (factory, per datasheet) |
| ピン 35 | TEST2 — Test mode 2 (factory, per datasheet) |
| ピン 36 | NC — Not connected (per datasheet) |
| ピン 37 | NC — Not connected (per datasheet) |
| ピン 38 | AVDD — Analog supply voltage |
| ピン 39 | AVDD — Analog supply voltage |
| ピン 40 | AGND — Analog ground (also exposed thermal pad) |
主な用途
ADC1410S105HN-C1 の用途: 7 件s: Communications Baseband Receiver, Medical Imaging Front End, Portable Digital Oscilloscope, Software-Defined Radio IF Sampling, Industrial Data Acquisition Module, Spectrum Analyzer / Digitizer, Radar / Lidar Baseband.
Communications Baseband Receiver
The ADC1410S105HN-C1 is well-matched for communications baseband receiver front ends where 14-bit dynamic range and 105 Msps sample rate are required to capture multi-carrier LTE and 3G signals. Its 1-channel pipelined core and LVDS DDR output mode support direct interface to FPGAs such as Xilinx Spartan-6 or Altera Cyclone IV, while the 40-HVQFN 6x6 mm package keeps board area small. The combination of selectable CMOS/LVDS DDR outputs lets designers trade off power versus interconnect simplicity when laying out dense multi-channel receivers, as documented in the ADC1410S family datasheet.
おすすめ
Medical Imaging Front End
In medical imaging systems such as ultrasound and digital X-ray detectors, the ADC1410S105HN-C1's 14-bit resolution and 105 Msps sampling rate digitize multi-MHz transducer analog signals with high dynamic range. The 1-channel pipelined architecture and HVQFN package suit compact ultrasound probe boards where PCB real estate is constrained. Compared with sigma-delta alternatives, the pipelined converter provides superior real-time bandwidth without the long filter-group-delay penalty, which is critical for B-mode and Doppler imaging timing alignment.
おすすめ
Portable Digital Oscilloscope
Benchtop and portable oscilloscopes in the 100-200 MHz bandwidth class rely on the ADC1410S105HN-C1's 14-bit resolution and 105 Msps to deliver high-vertical-resolution waveforms at competitive price points. The 40-HVQFN exposed thermal pad enables fanless cooling while dissipating the converter's moderate operating power. LVDS DDR mode is preferred for scopes with deep memory, since dual-data-rate clocking keeps the FPGA pin count manageable when capturing long records at full sample rate, according to the ADC1410S family datasheet.
おすすめ
Software-Defined Radio IF Sampling
Software-defined radio (SDR) platforms use the ADC1410S105HN-C1 to digitize intermediate frequency (IF) signals around 25-40 MHz with 105 Msps, providing a Nyquist bandwidth of 52.5 MHz suitable for capturing multiple amateur radio and commercial bands. The 14-bit pipelined architecture delivers dynamic range to receive weak signals adjacent to strong ones, and LVDS DDR outputs feed directly into FPGA transceivers. Compared to lower-bit-count converters, the 14-bit depth allows software demodulators to use the full dynamic range of the IF chain.
おすすめ
Industrial Data Acquisition Module
Industrial data-acquisition modules for vibration analysis, motor control feedback, and process instrumentation leverage the ADC1410S105HN-C1's industrial -40C to +85C temperature rating and 105 Msps sample rate. The single-channel pipelined architecture captures high-bandwidth vibration or sonar return signals with 14-bit resolution, while the compact 40-HVQFN footprint fits 4-quadrant or 8-channel multiplexed front ends for rotating-machinery monitoring. LVDS DDR outputs reduce ground-noise coupling across long industrial backplanes.
おすすめ
Spectrum Analyzer / Digitizer
Benchtop spectrum analyzers and wideband digitizers benefit from the ADC1410S105HN-C1's 14-bit resolution and 105 Msps rate, providing roughly 78 dB SFDR for spurious-free measurement of RF and baseband signals. The HVQFN package's exposed thermal pad dissipates converter heat in enclosed instrument enclosures with limited airflow. The selectable CMOS/LVDS DDR outputs allow designers to fan out to multiple FPGA channels without external logic-level translation, as documented in the ADC1410S family datasheet.
おすすめ
Radar / Lidar Baseband
Automotive and industrial radar/lidar baseband receivers at IF frequencies of 10-50 MHz use the ADC1410S105HN-C1 to digitize I/Q demodulated signals at 105 Msps with 14-bit resolution. The pipelined architecture provides low aperture jitter suitable for accurate amplitude measurement of FMCW chirp returns, and the 40-HVQFN 6x6 mm footprint suits radar ECU form factors. The LVDS DDR output mode preserves signal integrity across long board traces to FPGAs such as Artix-7 for real-time FFT processing.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC1410S105HN-C1 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC1410S125HN-C1 | ADC1410S080HN-C1 | ADC1410S065HN-C1 | ADC1010S105HN/C1:5 | ADC1012D080HN/C1:5 |
|---|---|---|---|---|---|---|
| Package | 40-HVQFN (6x6 mm, SOT618-6) | 40-HVQFN (6x6 mm, SOT618-6) - same | 40-HVQFN (6x6 mm, SOT618-6) - same | 40-HVQFN (6x6 mm, SOT618-6) - same | 40-HVQFN (6x6 mm, SOT618-6) - same | 40-HVQFN (6x6 mm, SOT618-6) - same |
| Brand | NXP Semiconductors (formerly IDT) | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Resolution | 14-bit | 14-bit | 14-bit | 14-bit | 10-bit | 10-bit |
| Sampling Rate | 105 Msps | 125 Msps (+19%) | 80 Msps (-24%) | 65 Msps (-38%) | 105 Msps (identical) | 80 Msps (-24%) |
| Number of Channels | 1 (single-ended) | 1 (single-ended) | 1 (single-ended) | 1 (single-ended) | 1 (single-ended) | 2 (dual-channel) |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | |
| Digital Output | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) |
| Control Interface | Serial SPI | Serial SPI | Serial SPI | Serial SPI | Serial SPI |
主な差別化要因
- Selectable CMOS or LVDS DDR digital output mode （vs ADC1010S105HN/C1:5)
- 14-bit resolution vs 10-bit in same 40-HVQFN footprint （vs ADC1012D080HN/C1:5)
- Single-channel pipelined architecture with proven 105 Msps throughput （vs AD9245)
設計ノート
Place AVDD decoupling capacitors (typically 10 nF + 100 nF X7R ceramic) within 2 mm of each AVDD/AGND pair on the 40-HVQFN exposed pad. Keep analog and digital return currents separated to a single ground star near the AGND pins, and stitch the digital ground on the PCB inner layer only at the AGND pins to avoid digital switching noise coupling into the analog input path. The exposed thermal pad must be soldered to a continuous copper pour of at least 1 sq cm for thermal relief at 105 Msps operating power.
Drive the analog input VIN through a wideband transformer (e.g., Mini-Circuits ADT1-1WT) or a low-noise differential driver for single-ended-to-differential conversion. Keep VIN trace length under 10 mm and surround it with continuous ground stitching vias to maintain 50 ohm characteristic impedance up to the package pin. The differential CLK+/CLK- pair should be length-matched within 0.5 mm and routed over a continuous ground reference to minimize clock jitter, which directly impacts ADC SNR.
Avoid connecting LVDS DDR outputs directly to CMOS-only FPGA banks - this creates common-mode voltage mismatch and can damage either driver or receiver. Confirm the FPGA bank supports LVDS-25 signaling when using LVDS DDR mode. Also, do not violate the absolute maximum analog input range listed in the datasheet; over-driving VIN with signals outside AVDD + 0.3 V to AGND - 0.3 V can latch-up the input ESD structure. Always sequence AVDD before VIN is applied at power-up, per the datasheet recommended power-up sequence.
コンプライアンス情報
RoHS compliance per HVQFN SOT618-6 (MO-220) plastic package declaration; industrial-grade screening level only - no AEC-Q100 automotive qualification available for this part number.
