LTC2141CUP-14 - 14-Bit 40Msps Dual ADC, 64-QFN | Analog Devices
部品番号: LTC2141CUP-14 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.65 | $346.50 |
| 100 | $30.8 | $3,080.00 |
| 500 | $27.45 | $13,725.00 |
| 1,000 | $24.1 | $24,100.00 |
| 3,000 | $21.55 | $64,650.00 |
LTC2141CUP-14 概要
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous analog voltages into discrete digital codes at a specified sampling rate. Dual ADCs integrate two synchronized sample-and-hold front ends and two pipelined conversion cores on a single die, enabling simultaneous sampling of two analog channels with matched gain, offset, and aperture delay. They sit within the broader hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. The pipelined architecture used in the LTC2141-14 family balances high sample rate (tens to hundreds of Msps) with low power consumption, making it the dominant choice for communications, imaging, and instrumentation front ends.
Key features of the LTC2141CUP-14 include a choice of full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS digital outputs for trade-offs between pin count, board area, and EMI immunity. The device supports both differential and single-ended analog inputs, accepts parallel or serial programming through a simple SPI-like interface, and operates from a single 1.8 V supply. Low power consumption and excellent AC performance (high SNR and SFDR) make it equally suitable for portable, multi-channel data acquisition systems and for dense baseband capture in communications infrastructure.
Typical applications include multi-channel communications receivers, portable and battery-powered instrumentation, medical imaging front ends, radar signal processing, and general-purpose high-speed data acquisition. When designing with this part, observe the recommended input common-mode voltage and drive the analog inputs through a wideband transformer or low-noise op-amp driver to preserve SFDR; insufficient analog input bandwidth is the most common root cause of degraded ENOB in pipelined ADC designs.
ドロップイン代替品: LTC2141CUP-14 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2141CUP-14 （同一形状・フットプリント） — 相違点: Input Type, Package, Resolution, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2140CUP-14
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2142CUP-14
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2141IUP-14
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2141CUP-14#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2141CUP-14#TRPBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2180IUP
✅ ドロップイン✓ 在庫あり
$48 / 個
データシートを見る →LTC2141CUP-14 最大定格＆電気的特性
| Manufacturer | Analog Devices (formerly Linear Technology) |
| Part Family | LTC2140-14 / LTC2141-14 / LTC2142-14 (14-bit, 40 / 65 Msps dual ADCs) |
| 分解能 | 14 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| サンプリングレート | 40 MSPS |
| Architecture | Pipelined |
| Input Type | Differential, Single-Ended |
| Data Interface | LVDS - Parallel, Parallel CMOS |
| INL (typical) | ±1 LSB |
| DNL (typical) | ±0.3 LSB |
| Missing Codes | None over temperature |
| Transition Noise | 1.2 LSB RMS |
| Output Modes | Full-rate CMOS, DDR CMOS, or DDR LVDS |
| Output Supply (OVDD) | 1.2 V to 1.8 V |
| 電源電圧 | 1.8 V (analog and digital core) |
| パッケージ | 64-pin QFN (UP) 9x9 mm |
| 実装タイプ | Surface Mount |
| 動作温度 | 0C to +70C (commercial 'C' grade) |
| RoHS ステータス | Compliant (PBF suffix) |
LTC2141CUP-14 ピン構成
| ピン 1 | GND — Ground |
| ピン 2 | GND — Ground |
| ピン 3 | AIN1+ — Channel 1 analog input, positive |
| ピン 4 | AIN1- — Channel 1 analog input, negative |
| ピン 5 | AIN2+ — Channel 2 analog input, positive |
| ピン 6 | AIN2- — Channel 2 analog input, negative |
| ピン 7 | VCM — Common-mode voltage output |
| ピン 8 | REF — Reference voltage decoupling |
| ピン 9 | GND — Ground |
| ピン 10 | VDD — 1.8 V analog supply |
| ピン 11 | GND — Ground |
| ピン 12 | SENSE — Reference configuration |
| ピン 13 | GND — Ground |
| ピン 14 | OGND — Output driver ground |
| ピン 15 | OVDD — Output driver supply (1.2 V to 1.8 V) |
| ピン 16 | CLK+ — Clock input, positive |
| ピン 17 | CLK- — Clock input, negative |
| ピン 18 | D0+ / DDR_LVDS — Output bit / LVDS pair |
| ピン 19 | D0- / DDR_LVDS — Output bit / LVDS pair |
| ピン 20 | D1+ / DDR_LVDS — Output bit / LVDS pair |
| ピン 21 | D1- / DDR_LVDS — Output bit / LVDS pair |
| ピン 22 | D2+ / DDR_LVDS — Output bit / LVDS pair |
| ピン 23 | D2- / DDR_LVDS — Output bit / LVDS pair |
| ピン 24 | D3+ / DDR_LVDS — Output bit / LVDS pair |
| ピン 25 | D3- / DDR_LVDS — Output bit / LVDS pair |
| ピン 26 | D4+ / DDR_LVDS — Output bit / LVDS pair |
| ピン 27 | D4- / DDR_LVDS — Output bit / LVDS pair |
| ピン 28 | D5+ / DDR_LVDS — Output bit / LVDS pair |
| ピン 29 | D5- / DDR_LVDS — Output bit / LVDS pair |
| ピン 30 | D6+ / DDR_LVDS — Output bit / LVDS pair |
| ピン 31 | D6- / DDR_LVDS — Output bit / LVDS pair |
| ピン 32 | D7+ / DDR_LVDS — Output bit / LVDS pair |
| ピン 33 | D7- / DDR_LVDS — Output bit / LVDS pair |
| ピン 34 | D8+ / DDR_LVDS — Output bit / LVDS pair |
| ピン 35 | D8- / DDR_LVDS — Output bit / LVDS pair |
| ピン 36 | D9+ / DDR_LVDS — Output bit / LVDS pair |
| ピン 37 | D9- / DDR_LVDS — Output bit / LVDS pair |
| ピン 38 | D10+ / DDR_LVDS — Output bit / LVDS pair |
| ピン 39 | D10- / DDR_LVDS — Output bit / LVDS pair |
| ピン 40 | D11+ / DDR_LVDS — Output bit / LVDS pair |
| ピン 41 | D11- / DDR_LVDS — Output bit / LVDS pair |
| ピン 42 | D12+ / DDR_LVDS — Output bit / LVDS pair |
| ピン 43 | D12- / DDR_LVDS — Output bit / LVDS pair |
| ピン 44 | D13+ / DDR_LVDS — Output bit / LVDS pair |
| ピン 45 | D13- / DDR_LVDS — Output bit / LVDS pair |
| ピン 46 | CLKOUT+ / FR — Clock output / frame |
| ピン 47 | CLKOUT- / FR — Clock output / frame complement |
| ピン 48 | OGND — Output driver ground |
| ピン 49 | OVDD — Output driver supply |
| ピン 50 | SDO — Serial data output |
| ピン 51 | SDI — Serial data input |
| ピン 52 | SCK — Serial clock |
| ピン 53 | CS — Chip select |
| ピン 54 | RESET — Reset input |
| ピン 55 | PD — Power-down input |
| ピン 56 | MODE — Output mode select (CMOS/DDR/LVDS) |
| ピン 57 | OGND — Output driver ground |
| ピン 58 | OVDD — Output driver supply |
| ピン 59 | GND — Ground |
| ピン 60 | VDD — 1.8 V analog supply |
| ピン 61 | GND — Ground |
| ピン 62 | GND — Ground |
| ピン 63 | NC — Not connected (per datasheet) |
| ピン 64 | EPAD — Exposed thermal pad - must be soldered to ground plane |
主な用途
LTC2141CUP-14 の用途: 6 件s: Multi-Channel Communications Receiver, Portable Battery-Powered Instrumentation, Medical Imaging Front End, Radar Signal Processing, General-Purpose High-Speed Data Acquisition, Industrial Automation and Control.
Multi-Channel Communications Receiver
Dual simultaneous-sampling 40 MSPS capture in a compact 9x9 mm 64-QFN suits diversity and MIMO baseband chains. The two matched ADC channels share a single clock, preserving gain, offset, and aperture delay to within tight tolerances required for I/Q demodulation. DDR-LVDS or CMOS outputs interface directly to FPGAs that perform digital downconversion. Excellent SFDR and SNR at IF frequencies up to 20 MHz make this part a strong fit for software-defined radio baseband capture.
おすすめ
Portable Battery-Powered Instrumentation
Low-power dual pipelined architecture lets engineers build two-channel oscilloscopes, spectrum analyzers, or data loggers without the thermal burden of high-speed converters. The separate 1.2 V to 1.8 V OVDD simplifies direct connection to modern low-power FPGAs, while ±1 LSB INL and 1.2 LSB RMS transition noise preserve measurement fidelity at 14-bit resolution. The commercial 0C to +70C temperature range and small 64-QFN footprint help shrink handheld form factors.
おすすめ
Medical Imaging Front End
Dual simultaneous sampling through matched front ends captures ultrasound echo pairs with identical time alignment, critical for beamforming and Doppler processing. The 40 MSPS sample rate comfortably digitizes ultrasound IF bandwidths up to ~18 MHz, and the pipelined core delivers the linearity required for tissue harmonic imaging. LVDS outputs minimize digital crosstalk into sensitive analog front-end circuits, helping preserve the low noise floor required by diagnostic-grade imaging systems.
おすすめ
Radar Signal Processing
Two synchronized ADC channels digitize in-phase and quadrature IF outputs from a radar downconverter with matched timing, eliminating skew errors that would otherwise corrupt phase-derived velocity calculations. The 40 MSPS throughput supports narrowband surveillance radar IFs while the ±1 LSB INL preserves amplitude fidelity for target classification. The 64-QFN package has the thermal headroom and ground-plane footprint needed for ruggedized defense or weather-radar installations.
おすすめ
General-Purpose High-Speed Data Acquisition
Two 40 MSPS, 14-bit channels fit PCIe, USB, or LXI-based DAQ cards where compact footprint and matched channels matter more than absolute maximum sample rate. The serial/parallel programming interface and CMOS/LVDS output modes simplify host-FPGA integration, while no-missing-codes over temperature and 1.2 LSB RMS transition noise deliver repeatable DC and AC measurements. Reuse the same PCB for the LTC2140-14 (25 MSPS) or LTC2142-14 (65 MSPS) for product-line scaling.
おすすめ
Industrial Automation and Control
Dual simultaneous sampling lets a single converter digitize both halves of a differential sensor pair - such as the outputs of a Wheatstone bridge or a current-shunt differential amplifier - with synchronized clocks and matched gain. The commercial LTC2141CUP-14 supports 0C to +70C operation common in factory-floor enclosures, and the industrial LTC2141IUP-14 extends the range to -40C to +85C with no PCB change. Industrial compliance (RoHS, REACH) supports global equipment certification.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2141CUP-14 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2140CUP-14 | LTC2142CUP-14 | LTC2141IUP-14 | LTC2141CUP-14#PBF | LTC2141CUP-14#TRPBF | LTC2180IUP |
|---|---|---|---|---|---|---|---|
| Package | 64-QFN (UP) 9x9 mm | 64-QFN (UP) 9x9 mm - same | 64-QFN (UP) 9x9 mm - same | 64-QFN (UP) 9x9 mm - same | 64-QFN (UP) 9x9 mm - same | 64-QFN (UP) 9x9 mm - same | 64-QFN (UP) - same family footprint |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 16 bit |
| Sample Rate | 40 MSPS | 25 MSPS | 65 MSPS | 40 MSPS | 40 MSPS | 40 MSPS | 105 MSPS |
| Number of Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) |
| Output Modes | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | ||
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C | 0C to +70C | -40C to +85C (industrial) | -40C to +85C (industrial) | ||
| RoHS Status | Compliant (PBF suffix) | Compliant | Compliant | Compliant | Compliant |
主な差別化要因
- True 14-bit performance with no missing codes over temperature （vs LTC2159IUK)
- Pin-compatible family spanning 25 to 65 MSPS （vs LTC2180IUP)
- Dual simultaneous-sampling on a single die （vs LTC2141IUP-14 (industrial variant))
- Flexible CMOS/DDR-CMOS/DDR-LVDS output modes （vs LTC2140CUP-14)
設計ノート
Drive the analog inputs (AIN1±, AIN2±) through a wideband, low-distortion driver such as a transformer or high-speed op-amp (e.g., AD8475 or AD8138) to preserve ENOB at the full 40 MSPS sample rate. Pipelined ADCs are extremely sensitive to analog input bandwidth; a 3 dB reduction in driver bandwidth will noticeably degrade SNR and SFDR above 10 MHz IF inputs. Keep the input traces 50 ohm controlled-impedance and length-matched within 250 microseconds of aperture.
The 64-QFN exposed thermal pad (EPAD, pin 64) MUST be soldered to a continuous, low-impedance ground plane to meet published thermal and electrical performance. Splitting the EPAD or using only a few thermal vias degrades the internal thermal path and can shift reference voltages, causing missing codes at temperature. Recommended practice is a 5x5 array of 12 mil (0.3 mm) thermal vias tying the EPAD to an internal ground plane.
Use separate, well-decoupled analog (VDD = 1.8 V) and output driver (OVDD = 1.2 V to 1.8 V) supplies. Place 1 nF and 10 uF X7R ceramic bypass capacitors within 5 mm of each VDD/OVDD pin. If the analog and output driver rails share an LDO, isolate them with ferrite beads and bulk capacitance to prevent output switching noise from corrupting the analog front end.
Do not exceed the absolute maximum analog input range (typically -0.3 V to VDD + 0.3 V) without input clamping - overdrive can permanently damage the ADC. Avoid using the internal reference for systems that require 14-bit absolute accuracy across production; instead, use the external reference option (SENSE pin) with a low-drift reference such as the LTC6655. Finally, route the LVDS output pairs as tightly-coupled, length-matched 100 ohm differential pairs to preserve signal integrity at DDR rates.
Keep digital outputs and clock traces physically separated from analog input traces to avoid digital-to-analog coupling. Route the clock (CLK±) signal with 50 ohm controlled impedance and place a 100 ohm differential termination at the receiver end. Estimate: total clock trace length should be kept below 25 mm and routed away from the analog inputs to minimize jitter-induced SNR degradation (target SNR floor 73 dBFS at 10 MHz input).
コンプライアンス情報
RoHS compliance is indicated by the #PBF suffix on factory-packed orders. The part is not AEC-Q100 qualified - it is a commercial/industrial-grade data converter intended for non-automotive applications. Halogen-free status not explicitly stated in the provided web data.
