LTC2180IUP - 16-Bit 25Msps Dual ADC | Analog Devices
部品番号: LTC2180IUP ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $75 | $75.00 |
| 10 | $67.5 | $675.00 |
| 100 | $60 | $6,000.00 |
| 500 | $54 | $27,000.00 |
| 1,000 | $48 | $48,000.00 |
LTC2180IUP 概要
Background Knowledge: An ADC (Analog-to-Digital Converter) is a semiconductor device that converts continuous analog signals into discrete digital codes. Dual ADCs contain two independent converter channels that sample simultaneously, which is essential when the relative phase between two signals carries information (for example, I/Q baseband signals in a radio receiver, or paired sensor channels in sonar and vibration analysis). The LTC2180 family sits within the broader hierarchy: ADC -> data converter -> signal chain IC -> mixed-signal semiconductor.
Key features include 25 Msps sampling per channel, simultaneous sampling of both inputs, ultralow jitter of 0.07 ps RMS that enables IF undersampling, an internal common-mode reference buffer, and a flexible CMOS/LVDS digital output bus. The pipelined architecture delivers low latency while maintaining 16-bit resolution at full throughput. Total power dissipation is approximately 250 mW per channel at full rate.
Typical applications include diversity receivers and I/Q digitizers in software-defined radio, multi-channel ultrasound front ends, precision data acquisition, wideband spectrum analyzers, and medical imaging subsystems. The wide input bandwidth and excellent SFDR make it suitable for direct-IF sampling.
Design consideration: because both channels share a common clock and reference, layout must keep analog and digital grounds separated under the exposed pad. Aggressive LC filtering on the analog AVDD supply is critical to maintain SNR at high input frequencies.
This page synthesizes distributor pricing, drop-in same-package alternatives from the same LTC family, and practical design notes not consolidated in the manufacturer datasheet, providing decision-ready information for engineers selecting a 16-bit dual ADC for a multi-channel signal chain.
ドロップイン代替品: LTC2180IUP — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2180IUP （同一形状・フットプリント） — 相違点: Package, Operating Temperature Range, Input Type, SNR, Resolution.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2180CUP
✅ ドロップイン✓ 在庫あり
$41.72 / 個
データシートを見る →LTC2181IUP
✅ ドロップイン✓ 在庫あり
$25.2 / 個
データシートを見る →LTC2182IUP
✅ ドロップイン✓ 在庫あり
$105.93 / 個
データシートを見る →LTC2175IUKG-12
✅ ドロップイン✓ 在庫あり
$28.1 / 個
データシートを見る →LTC2145CUP-12
✅ ドロップイン✓ 在庫あり
$26.4 / 個
データシートを見る →LTC2156IUP-14
✅ ドロップイン✓ 在庫あり
$134.1 / 個
データシートを見る →LTC2180IUP 最大定格＆電気的特性
| 分解能 | 16 bits |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sampling Rate (per channel) | 25 Msps |
| Architecture | Pipelined |
| Input Type | Differential |
| SNR | 77 dB |
| SFDR | 90 dB |
| Aperture Jitter | 0.07 ps RMS |
| Supply Voltage (AVDD/DVDD) | 1.8 V typ |
| Digital Output | CMOS or LVDS selectable |
| パッケージ | 64-QFN (9x9 mm) with exposed pad |
| 実装タイプ | Surface Mount |
| 動作温度範囲 | -40C to +85C (industrial, "I" suffix) |
| RoHS ステータス | Compliant |
LTC2180IUP ピン構成
| ピン 1 | AIN1+ — Channel 1 analog input positive (differential) |
| ピン 2 | AIN1- — Channel 1 analog input negative (differential) |
| ピン 3 | GND — Analog ground reference |
| ピン 4 | AIN2+ — Channel 2 analog input positive (differential) |
| ピン 5 | AIN2- — Channel 2 analog input negative (differential) |
| ピン 6 | REFT — Reference top (output) |
| ピン 7 | REFM — Reference mid (output) |
| ピン 8 | REFB — Reference bottom (output) |
| ピン 9 | REFP — Reference positive (drive with external reference) |
| ピン 10 | REFN — Reference negative (drive with external reference) |
| ピン 11 | VCM — Common-mode voltage buffer output |
| ピン 12 | AVDD — Analog 1.8V supply |
| ピン 13 | AVDD — Analog 1.8V supply |
| ピン 14 | GND — Analog ground |
| ピン 15 | AVDD — Analog 1.8V supply |
| ピン 16 | GND — Analog ground |
| ピン 17 | ENC+ — Encode clock input positive |
| ピン 18 | ENC- — Encode clock input negative |
| ピン 19 | GND — Clock ground |
| ピン 20 | AVDD — Analog 1.8V supply |
| ピン 21 | GND — Analog ground |
| ピン 22 | NC — Not connected |
| ピン 23 | NC — Not connected |
| ピン 24 | DVDD — Digital 1.8V supply |
| ピン 25 | DVDD — Digital 1.8V supply |
| ピン 26 | GND — Digital ground |
| ピン 27 | OGND — Output driver ground (LVDS/CMOS) |
| ピン 28 | OVDD — Output driver supply |
| ピン 29 | MODE — Output mode / data format select |
| ピン 30 | CS — Chip select (SPI configuration) |
| ピン 31 | SCK — Serial clock (SPI configuration) |
| ピン 32 | SDI — Serial data input (SPI configuration) |
| ピン 33 | SDO — Serial data output (SPI configuration) |
| ピン 34 | DFMT — Data format select: 2's complement / offset binary |
| ピン 35 | LVDSCMOS — LVDS / CMOS output driver select |
| ピン 36 | CLKDIV — Clock divider select |
| ピン 37 | RAND — Data output randomizer enable |
| ピン 38 | OUT1A_P — Channel 1 LVDS data positive (or CMOS bit A) |
| ピン 39 | OUT1A_N — Channel 1 LVDS data negative (or CMOS bit /A) |
| ピン 40 | OUT1B_P — Channel 1 LVDS data positive (or CMOS bit B) |
| ピン 41 | OUT1B_N — Channel 1 LVDS data negative (or CMOS bit /B) |
| ピン 42 | DCO_P — Data clock output positive (LVDS) |
| ピン 43 | DCO_N — Data clock output negative (LVDS) |
| ピン 44 | FR_P — Frame output positive (LVDS) |
| ピン 45 | FR_N — Frame output negative (LVDS) |
| ピン 46 | OUT2A_P — Channel 2 LVDS data positive (or CMOS bit A) |
| ピン 47 | OUT2A_N — Channel 2 LVDS data negative (or CMOS bit /A) |
| ピン 48 | OUT2B_P — Channel 2 LVDS data positive (or CMOS bit B) |
| ピン 49 | OUT2B_N — Channel 2 LVDS data negative (or CMOS bit /B) |
| ピン 50 | GND — Digital ground |
| ピン 51 | DVDD — Digital 1.8V supply |
| ピン 52 | GND — Digital ground |
| ピン 53 | NC — Not connected |
| ピン 54 | NC — Not connected |
| ピン 55 | NC — Not connected |
| ピン 56 | NC — Not connected |
| ピン 57 | NC — Not connected |
| ピン 58 | NC — Not connected |
| ピン 59 | NC — Not connected |
| ピン 60 | NC — Not connected |
| ピン 61 | SENSE — Voltage sense pin (analog supply monitor) |
| ピン 62 | VAUX — Auxiliary voltage (decoupling pin) |
| ピン 63 | GND — Analog ground |
| ピン 64 | GND — Analog ground (tied to EPAD) |
主な用途
LTC2180IUP の用途: 6 件s: Software-Defined Radio (SDR) Diversity Receivers, Multi-Channel Ultrasound Imaging, Wideband Spectrum Analyzers, Industrial Data Acquisition (DAQ) Modules, Doppler Radar and Lidar Receivers, Multi-Channel Vibration & Acoustic Monitoring.
Software-Defined Radio (SDR) Diversity Receivers
The LTC2180IUP is a strong fit for diversity SDR front ends because both ADC channels sample simultaneously, preserving the relative phase information needed for I/Q demodulation. Its 90 dB SFDR and 77 dB SNR at 25 Msps clean up the crowded RF spectrum, while 0.07 ps RMS ultralow aperture jitter allows direct undersampling of IF stages without SFDR degradation. Power consumption is well below 1 W for a dual-channel receiver, easing thermal design in portable SDR platforms. The 64-QFN (9x9) exposed-pad package supports dense multi-channel tuner arrays, and the CMOS/LVDS selectable output simplifies FPGA interface design for software-defined baseband processing.
おすすめ
Multi-Channel Ultrasound Imaging
In multi-channel medical ultrasound, the LTC2180IUP's simultaneous sampling preserves the precise inter-channel delay required for beamforming. Its 16-bit resolution captures the wide dynamic range from weak echoes to strong specular reflections, while 77 dB SNR preserves grayscale depth. The 25 Msps rate is well-matched to 5-15 MHz transducer-bandwidth inputs after the LNA and TGC stage. The 64-QFN (9x9) package and pipelined architecture keep per-channel power low so 64- and 128-channel probe designs remain thermally manageable in compact carts and portable scanners.
おすすめ
Wideband Spectrum Analyzers
The LTC2180IUP suits real-time and swept spectrum analyzers that need low-noise digitizing at 25 Msps in a 9x9 mm QFN. The 90 dB SFDR preserves weak spurs near large signals during harmonic and IMD testing, and the wide input bandwidth supports direct sampling of low-IF stages in modern FFT analyzers. The simultaneous dual channels let engineers digitize both input and trigger/alignment paths without skew, simplifying calibration routines. With LVDS output to an FPGA-based FFT engine, designers can build analyzers that meet lab-grade dynamic-range specs in a compact bench footprint.
おすすめ
Industrial Data Acquisition (DAQ) Modules
Industrial DAQ modules benefit from the LTC2180IUP because its -40C to +85C industrial temp range covers factory-floor conditions and its 16-bit resolution handles transducer-level dynamic range. The simultaneous dual-channel capture is ideal for paired sensor measurements (strain gauges, accelerometers, and vibration probes). At 25 Msps the device digitizes not only steady-state process signals but also transient surge events down to microseconds, enabling predictive-maintenance algorithms. The 64-QFN (9x9) exposed-pad package ensures good thermal coupling in sealed module housings.
おすすめ
Doppler Radar and Lidar Receivers
For Doppler radar and lidar receiver IF stages, the LTC2180IUP delivers 16-bit / 25 Msps dual-channel conversion that supports coherent I/Q detection. The 0.07 ps RMS jitter preserves phase coherence of the I/Q baseband, directly impacting velocity resolution. Both channels sample simultaneously, enabling real-time I/Q processing in stationary or moving platforms. Low power consumption keeps battery-powered lidar units efficient, and the small 64-QFN (9x9) footprint eases integration into automotive and UAV sensor pods that demand tight PCB real estate.
おすすめ
Multi-Channel Vibration & Acoustic Monitoring
Predictive-maintenance and acoustic-emission systems leverage the LTC2180IUP's dual-channel simultaneity to capture correlated vibration and acoustic signatures across multiple accelerometers or microphones. The 16-bit resolution and 77 dB SNR reveal subtle fault patterns such as bearing-race spalling and gear-mesh chatter. The 25 Msps sample rate gives engineers significant anti-aliasing margin without requiring steep analog filter orders. The exposed-pad QFN package spreads self-heating across the PCB copper pour, allowing dense sensor-cluster boards to run continuously without thermal throttling.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2180IUP — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2180CUP | LTC2181IUP | LTC2182IUP | LTC2145CUP-12 | LTC2156IUP-14 |
|---|---|---|---|---|---|---|
| Package | 64-QFN (9x9 mm) | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 16 bits | 16 bits | 16 bits | 16 bits | 14 bits | 14 bits |
| Sample Rate (per channel) | 25 Msps | 25 Msps | 40 Msps | 65 Msps | 65 Msps | 80 Msps |
| Number of Channels | 2 (dual) | 2 | 2 | 2 | 1 (single) | 2 |
| Temperature Grade | Industrial -40C to +85C | Commercial 0C to +70C | Industrial -40C to +85C | Industrial -40C to +85C | Commercial | Industrial |
| SNR | 77 dB | 77 dB | 77 dB | 76 dB | 73 dB | 68 dB |
| SFDR | 90 dB | 90 dB | 90 dB | 88 dB | 88 dB | 80 dB |
主な差別化要因
- Dual-channel simultaneous sampling with ultralow 0.07 ps RMS jitter （vs LTC2145CUP-12)
- Lower sample rate at lower power and price than the LTC2182 （vs LTC2182IUP)
- Industrial temperature range over commercial grade alternative （vs LTC2180CUP)
- 16-bit resolution at 25 Msps maintains SNR vs faster lower-res alternatives （vs LTC2156IUP-14)
設計ノート
The LTC2180IUP requires separate analog (AVDD) and digital (DVDD/OVDD) 1.8V rails that must be decoupled aggressively near the pins. Estimated: assuming 250 mW total dissipation and a theta_JA in the 30-35 C/W range for the 64-QFN (9x9) mounted on a 4-layer PCB, junction temperature rise above ambient stays under 10C at room temperature. Place 0.1 uF MLCCs as close as possible to each AVDD/DVDD pin and at least one 10 uF tantalum or polymer bulk cap per rail.
The exposed thermal pad is the primary heat path and the substrate tie to analog ground. Solder the EPAD to a continuous copper pour that is stitched with multiple vias to the internal ground plane. Keep analog input traces, clock traces, and LVDS output traces on separate layers to avoid coupling; use 100-ohm differential impedance for LVDS outputs and 50-ohm controlled impedance for the ENC clock input. Avoid routing digital outputs directly under the package to prevent digital-to-analog feedback.
Drive the ENC/ENC-/ENCCLK pair as a differential pair with matched length and a low-jitter clock source such as the AD9516. Ultralow aperture jitter (0.07 ps RMS) is only meaningful if the input clock is low-jitter; any clock degradation above 1 ps RMS directly reduces SNR at high input frequencies. Use an isolating clock buffer or transformer if the LVDS output data clock or FPGA clock distribution cannot guarantee sub-picosecond jitter.
Drivers for the AIN+/AIN- inputs must be low-distortion at the signal frequency band, with output balance better than -40 dBFS second harmonic to avoid compression of the ADC's true SFDR. Estimated: a common-mode choke plus 50-ohm series terminations at each pin yields the cleanest results on wideband inputs. Do not run the LVDS outputs at OVDD above 1.9V when connected to lower-voltage FPGAs without level shifters. Avoid hot-plugging the analog inputs without proper sequencing, since unpowered ADC inputs can drive current into the AVDD rail.
Although the LTC2180IUP is rated for the industrial temperature range, the user must still respect maximum junction temperature (typically 125C or 150C depending on datasheet version). Estimated thermal resistance for the 64-QFN (9x9) with EPAD on a 4-layer JEDEC test board is around 30 C/W. In a sealed enclosure with limited airflow, derate sample rate or supply voltage to maintain margin; consider the LTC2180CUP commercial-grade variant for benign thermal environments.
コンプライアンス情報
RoHS and lead-free (PBF suffix) per Analog Devices product page. Not AEC-Q100 qualified; for automotive imaging or radar choose an automotive-graded ADC family such as the ADI ADI9204/ADI9384 line.
