LTC2171IUKG-12 - 12-Bit 40Msps Quad ADC, 1.8V Serial LVDS | ADI
部品番号: LTC2171IUKG-12 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $36.41 | $36.41 |
| 10 | $32.77 | $327.70 |
| 100 | $29.13 | $2,913.00 |
| 500 | $26.21 | $13,105.00 |
| 1,000 | $23.3 | $23,300.00 |
LTC2171IUKG-12 概要
What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed successive-approximation architecture optimized for sample rates from a few MS/s to over 100 MS/s, where multiple low-resolution stages resolve each conversion in parallel. Pipelined ADCs are the workhorse of communications, instrumentation, and multichannel data-acquisition designs because they achieve excellent dynamic range at moderate power budgets and are easily replicated for simultaneous multi-channel acquisition. In the broader product taxonomy, the LTC2171IUKG-12 is an ADC -> data converter -> signal chain IC -> semiconductor device.
Key specifications include +/-0.3 LSB INL (typical) and +/-0.1 LSB DNL (typical) with no missing codes over the full temperature range, transition noise of 0.3 LSB RMS, and integrated shutdown and nap modes controlled through a serial SPI port. The 52-pin QFN-52 (UKG) 7mm x 8mm package is pin-compatible with 14-bit and 12-bit speed grades in the LTC2170/2171/2172 family, giving designers a clear upgrade path across resolution and sample-rate combinations.
The serial LVDS interface reduces FPGA pin count and PCB routing complexity compared with parallel CMOS outputs, allowing longer trace lengths without compromising timing. Pairing with a low-jitter differential clock and an Analog Devices ADA4927 driver typically achieves optimum SFDR at intermediate frequencies used in wireless baseband, ultrasound beamformers, and portable test instrumentation.
Typical applications include medical ultrasound imaging, communications infrastructure receivers, multichannel data acquisition, and portable battery-powered test equipment. The device is also widely deployed in digital oscilloscopes and spectrum analyzers where density of analog front-end channels and low per-channel power are critical.
When designing with this device, route LVDS pairs as 100 ohm differential lines with matched length, place the analog input RC network as close to the AI pins as possible, and provide a low-noise 1.8V rail with adequate decoupling to preserve SFDR. The shutdown and nap modes should be used in battery-powered designs to reduce quiescent draw when the converter is idle.
This page aggregates distributor pricing, drop-in alternatives, and practical design notes for the LTC2171IUKG-12 that complement the official Analog Devices datasheet for faster component evaluation.
ドロップイン代替品: LTC2171IUKG-12 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2171IUKG-12 （同一形状・フットプリント） — 相違点: Package, Operating Temperature Range, Input Type, Number of Channels, Sampling Rate.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2171CUKG-12
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$24 / 個
データシートを見る →LTC2171CUKG-14
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$26.75 / 個
データシートを見る →LTC2170CUKG-12
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$20.65 / 個
データシートを見る →LTC2172IUKG-12
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$33.1 / 個
データシートを見る →ADS6425IRGCR
✅ ドロップイン✓ 在庫あり
$23.1 / 個
データシートを見る →ADS6424IRGC25
✅ ドロップイン✓ 在庫あり
$31.2 / 個
データシートを見る →ADS6422IRGC25
✅ ドロップイン✓ 在庫あり
$14.95 / 個
データシートを見る →LTC2171IUKG-12 最大定格＆電気的特性
| 分解能 | 12 bit |
| Number of Channels | 4 |
| サンプリングレート | 40 MS/s |
| Architecture | Pipelined |
| Analog Supply Voltage | 1.8 V (single supply) |
| Integral Nonlinearity (INL) | +/-0.3 LSB (typical) |
| Differential Nonlinearity (DNL) | +/-0.1 LSB (typical) |
| Missing Codes | None over temperature |
| Transition Noise | 0.3 LSB RMS |
| Full Power Input Bandwidth | 800 MHz |
| Digital Output | Serial LVDS (1-lane or 2-lane mode) |
| Power Management Modes | Shutdown and Nap modes |
| Configuration Interface | Serial SPI port |
| Analog Input | Differential |
| パッケージ | 52-pin QFN (UKG) 7mm x 8mm |
| Family Compatibility | Pin-compatible 14-bit and 12-bit grades (LTC2170/LTC2171/LTC2172 family) |
| RoHS ステータス | Compliant (#PBF suffix) |
| Operating Temperature (I grade) | -40C to +85C (industrial) |
LTC2171IUKG-12 ピン構成
| ピン 1 | GND — Ground return (also bonded to exposed pad) |
| ピン 2 | VCM — Common-mode voltage output for analog inputs |
| ピン 3 | AIN1+ — Differential analog input 1, positive |
| ピン 4 | AIN1- — Differential analog input 1, negative |
| ピン 5 | GND — Analog ground |
| ピン 6 | AIN2+ — Differential analog input 2, positive |
| ピン 7 | AIN2- — Differential analog input 2, negative |
| ピン 8 | GND — Analog ground |
| ピン 9 | AIN3+ — Differential analog input 3, positive |
| ピン 10 | AIN3- — Differential analog input 3, negative |
| ピン 11 | GND — Analog ground |
| ピン 12 | AIN4+ — Differential analog input 4, positive |
| ピン 13 | AIN4- — Differential analog input 4, negative |
| ピン 14 | GND — Analog ground |
| ピン 15 | VA — 1.8V analog supply |
| ピン 16 | VA — 1.8V analog supply |
| ピン 17 | VA — 1.8V analog supply |
| ピン 18 | GND — Analog ground |
| ピン 19 | ENC+ — Encode clock input, positive (LVDS) |
| ピン 20 | ENC- — Encode clock input, negative (LVDS) |
| ピン 21 | GND — Digital ground |
| ピン 22 | VD — 1.8V digital supply |
| ピン 23 | VD — 1.8V digital supply |
| ピン 24 | GND — Digital ground |
| ピン 25 | CS — SPI chip select (active low) |
| ピン 26 | SCK — SPI serial clock |
| ピン 27 | SDI — SPI serial data input |
| ピン 28 | SDO — SPI serial data output |
| ピン 29 | RESET — Hardware reset (active low) |
| ピン 30 | SHDN — Shutdown mode control |
| ピン 31 | NAP — Nap mode control |
| ピン 32 | GND — Digital ground |
| ピン 33 | OUT1+ — Channel 1 LVDS data output, positive |
| ピン 34 | OUT1- — Channel 1 LVDS data output, negative |
| ピン 35 | FR+ — Frame output LVDS, positive |
| ピン 36 | FR- — Frame output LVDS, negative |
| ピン 37 | OUT2+ — Channel 2 LVDS data output, positive |
| ピン 38 | OUT2- — Channel 2 LVDS data output, negative |
| ピン 39 | CLKOUT+ — LVDS clock output, positive |
| ピン 40 | CLKOUT- — LVDS clock output, negative |
| ピン 41 | OUT3+ — Channel 3 LVDS data output, positive |
| ピン 42 | OUT3- — Channel 3 LVDS data output, negative |
| ピン 43 | DCO+ — Data clock LVDS output, positive |
| ピン 44 | DCO- — Data clock LVDS output, negative |
| ピン 45 | OUT4+ — Channel 4 LVDS data output, positive |
| ピン 46 | OUT4- — Channel 4 LVDS data output, negative |
| ピン 47 | GND — Digital ground |
| ピン 48 | VD — 1.8V digital supply |
| ピン 49 | VD — 1.8V digital supply |
| ピン 50 | GND — Digital ground |
| ピン 51 | VA — 1.8V analog supply |
| ピン 52 | VA — 1.8V analog supply |
主な用途
LTC2171IUKG-12 の用途: 6 件s: Medical Ultrasound Imaging, Communications Multi-Channel Receiver, Multichannel Data Acquisition Systems, Digital Oscilloscope and Spectrum Analyzer Front End, Portable Test and Measurement Equipment, Phased-Array Radar and Beamforming.
Medical Ultrasound Imaging
The LTC2171IUKG-12 fits medical ultrasound systems because of its 4 simultaneously-sampling channels with 0.3 LSB RMS transition noise and 800 MHz input bandwidth. In a typical ultrasound beamformer each channel digitizes one element of a phased-array transducer at 40 Msps with 12-bit resolution, preserving phase coherence across channels for accurate beam steering. The serial LVDS output minimizes cable and PCB trace count between the analog front end and the FPGA-based beamformer, while the 1.8V supply keeps per-channel power low enough for portable cart-based systems. Use the LTC2172IUKG-12 family member when harmonics above 20 MHz must be captured.
おすすめ
Communications Multi-Channel Receiver
The LTC2171IUKG-12 suits communications receivers where 4 simultaneous 40 Msps channels digitize I/Q baseband or multi-antenna streams. Its serial LVDS output cuts FPGA pin count and PCB routing, which matters in dense MIMO radio cards. Driving each differential input through an ADA4927 driver preserves SFDR, while the on-chip SPI port lets designers fine-tune gain, offset, and channel modes at runtime. The 800 MHz input bandwidth allows direct IF sampling at intermediate frequencies commonly used in LTE and 5G NR base-station receivers.
おすすめ
Multichannel Data Acquisition Systems
For industrial and scientific data acquisition, the LTC2171IUKG-12 delivers four simultaneously-sampled 12-bit channels at 40 Msps in a small QFN-52 footprint. Industrial vibration analyzers, modal testing equipment, and multi-axis motion controllers benefit from the differential inputs and 0.3 LSB transition noise for clean harmonic capture of vibration signatures. The shutdown and nap modes reduce power when channels are not in use, which is useful in triggered transient recording applications where quiescent draw dominates thermal budgets.
おすすめ
Digital Oscilloscope and Spectrum Analyzer Front End
Digital oscilloscopes and spectrum analyzers use the LTC2171IUKG-12 to digitize up to four channels at 40 Msps simultaneously when capturing slow time-domain transients or low-bandwidth spectrum slices. The 12-bit resolution allows 4096 vertical quantization levels, and the serial LVDS interface simplifies routing between the analog board and the FPGA DSP. Designers commonly use the LTC2172IUKG-12 in higher-bandwidth scope channels, while keeping the same QFN-52 footprint and pinout to reuse the PCB layout.
おすすめ
Portable Test and Measurement Equipment
Battery-powered test instruments deploy the LTC2171IUKG-12 for its low per-channel power from a single 1.8V supply and its integrated shutdown and nap modes. Handheld oscilloscopes, spectrum analyzers, and field RF scanners use the four channels to maximize measurement capability while preserving battery runtime. The 800 MHz input bandwidth supports direct sampling of intermediate-frequency signals without an external downconverter, reducing BOM cost and board area.
おすすめ
Phased-Array Radar and Beamforming
The LTC2171IUKG-12 is well matched to phased-array radar and electronic-warfare receivers because its four simultaneously-sampling inputs preserve phase coherence across adjacent antenna channels. At 40 Msps with 12-bit resolution, the converter captures baseband I/Q at intermediate frequencies where jamming robustness matters. The serial LVDS output keeps digital traces off the antenna PCB, and the SPI port enables per-channel gain and offset trim across the array for the best beam-pattern side-lobe performance.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2171IUKG-12 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2171CUKG-12 | LTC2171CUKG-14 | LTC2170CUKG-12 | LTC2172IUKG-12 | ADS6425IRGCR | ADS6424IRGC25 |
|---|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Texas Instruments | Texas Instruments |
| Package | QFN-52 (UKG) 7x8 mm | QFN-52 (UKG) 7x8 mm - same | QFN-52 (UKG) 7x8 mm - same | QFN-52 (UKG) 7x8 mm - same | QFN-52 (UKG) 7x8 mm - same | QFN-52 (RGC) 7x7 mm | QFN-52 (RGC) 7x7 mm |
| Resolution | 12 bit | 12 bit - same | 14 bit (+17%) | 12 bit - same | 12 bit - same | 12 bit - same | 12 bit - same |
| Sampling Rate | 40 MS/s | 40 MS/s - same | 40 MS/s - same | 25 MS/s (-38%) | 65 MS/s (+62%) | 40 MS/s - same | 40 MS/s - same |
| Number of Channels | 4 | 4 - same | 4 - same | 4 - same | 4 - same | 4 - same | 4 - same |
| Digital Output | Serial LVDS (1-/2-lane) | Serial LVDS - same | Serial LVDS - same | Serial LVDS - same | Serial LVDS - same | Parallel LVDS | Parallel LVDS |
| Analog Supply | 1.8 V | 1.8 V - same | 1.8 V - same | 1.8 V - same | 1.8 V - same | 3.3 V | 3.3 V |
| Operating Temperature (I grade) | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
主な差別化要因
- Pin-compatible resolution and speed migration across LTC2170/2171/2172 （vs LTC2170CUKG-12)
- Industrial temperature range -40C to +85C （vs LTC2171CUKG-12)
- Serialized LVDS output saves FPGA pins vs parallel CMOS ADCs （vs ADS6425IRGCR)
設計ノート
Route the differential analog inputs (AINx+/AINx-) as a 100 ohm differential pair with matched length and continuous ground reference; place the anti-alias RC network as close as possible to the AI pins. The LVDS outputs and encode clock (ENC+/ENC-) are also LVDS and must be routed as 100 ohm differential pairs, kept away from noisy analog traces. Use a solid uninterrupted ground plane on layer 2 beneath the QFN-52 (UKG) package and stitch the perimeter with via fences around the analog section to maximize SFDR. Decouple each VA and VD pin with 100 nF X7R plus 10 uF bulk ceramic placed within 2 mm of the pin.
Power the LTC2171IUKG-12 from a clean 1.8V rail derived from a low-noise LDO such as ADP150, not from a switching converter directly. The sample-rate noise and timing jitter performance are dominated by supply noise; ripple above 10 mVpp on VA will degrade SNR. Estimated: at 40 Msps with four active channels, the ADC draws approximately 100-150 mA from VA; the 10 uF bulk ceramic plus a ferrite bead gives the required ripple suppression for targeted SNR.
Drive the encode clock with a low-jitter LVDS source such as the AD9516, with jitter below 200 fs RMS to avoid aperture-induced SNR loss at the ADC's 800 MHz input bandwidth. The clock line must be a 100 ohm differential pair with intra-pair skew kept under 5 ps to maintain optimum SFDR. Avoid using CMOS oscillators to drive ENC+/ENC- because their jitter will dominate converter noise.
Do not leave the shutdown or nap pins floating. The shutdown and nap modes must be pulled to logic-high or logic-low values explicitly through the SPI port or hard-wired GPIOs from the FPGA; floating the SHDN/NAP pins causes unintended partial power-down and unpredictable device behavior. Also note that the exposed pad of the QFN-52 must be soldered to a clean ground plane with multiple thermal vias for thermal dissipation.
コンプライアンス情報
RoHS and REACH compliant per the #PBF suffix and the Analog Devices product page. AEC-Q100 not relevant for industrial-grade A/D converters unless explicitly qualified; consult factory for automotive-grade derivatives.
