ADS6425IRGCR - 12-Bit 125MSPS Quad-Channel ADC | Texas Instruments
部品番号: ADS6425IRGCR ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $36.5 | $36.50 |
| 10 | $32.85 | $328.50 |
| 100 | $29.2 | $2,920.00 |
| 500 | $25.95 | $12,975.00 |
| 1,000 | $23.1 | $23,100.00 |
ADS6425IRGCR 概要
An analog-to-digital converter (ADC) is a data acquisition integrated circuit that converts continuous analog signals into discrete digital codes for downstream processing by DSPs, FPGAs, or microcontrollers. As a pipelined ADC, the ADS6425IRGCR uses a multi-stage architecture that converts input voltages through successive gain stages, with on-chip digital error correction, enabling high sampling rates while maintaining 12-bit linearity. Within the broader data converter hierarchy, this part belongs to the power-efficient, high-speed, multi-channel ADC category commonly used in communications, medical imaging, and industrial test systems.
Key performance features include 12-bit resolution, four differential input channels, 125 MSPS sampling per channel, LVDS serialized outputs with selectable doublets/quadruplets, an internal sample-and-hold, and an integrated clock stabilizer. The pipelined architecture provides low latency on the order of a few clock cycles and supports fine gain and offset adjustment per channel through dedicated registers.
The serialized LVDS interface allows multiple ADCs to share a common FPGA data bus, simplifying board layout and reducing FPGA pin count. The internal reference and high-impedance analog inputs simplify external signal conditioning, while the exposed thermal pad of the VQFN package provides a low theta-JA thermal path for reliable operation across the -40C to +85C industrial temperature range.
Typical applications for the ADS6425IRGCR include wireless communications base-station receivers, medical ultrasound beamformers, multi-channel data acquisition systems, radar and lidar front ends, and test and measurement instrumentation where simultaneous sampling of multiple channels is required.
When designing with this device, ensure clean analog input routing, adequate input bandwidth, and proper bypass of the 3.3 V AVDD and 1.8 V DVDD rails. The LVDS output pairs require 100 ohm differential termination at the receiver side for reliable high-speed operation.
This page synthesizes distributor pricing, drop-in alternatives within the same VQFN-64 (RGC) footprint, and practical design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: ADS6425IRGCR — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADS6425IRGCR （同一形状・フットプリント） — 相違点: Number of Channels, Resolution, Package, Input Type, Operating Temperature Range.
クイック比較ツール — 並列比較する代替部品を選択:
ADS6425IRGCT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS6424IRGCR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS6424IRGCT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS6423IRGCR
✅ ドロップイン✓ 在庫あり
$21.85 / 個
データシートを見る →ADS6422IRGCR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS6422IRGC25
✅ ドロップイン✓ 在庫あり
$14.95 / 個
データシートを見る →ADS6425IRGCR 最大定格＆電気的特性
| 分解能 | 12 bits |
| Number of Channels | 4 differential inputs |
| サンプリングレート | 125 MSPS per channel |
| Architecture | Pipelined |
| Analog Supply Voltage | 3.3 V (AVDD) |
| Digital Supply Voltage | 1.8 V (DVDD) |
| Data Output Interface | Serialized LVDS |
| パッケージ | 64-pin VQFN (RGC) 9x9 mm |
| 実装タイプ | Surface Mount |
| 動作温度範囲 | -40°C to +85°C (industrial) |
| Input Type | Differential |
| Sampling Mode | Simultaneous across 4 channels |
| MSLレベル | 3 (per JEDEC J-STD-020) |
| Lead-Free / RoHS Status | Lead-Free, RoHS Compliant |
| ハロゲンフリー | Yes |
ADS6425IRGCR ピン構成
| ピン 1 | AINP1 — Analog input 1 positive |
| ピン 2 | AINM1 — Analog input 1 negative |
| ピン 3 | VCM — Common-mode voltage output |
| ピン 4 | AINP2 — Analog input 2 positive |
| ピン 5 | AINM2 — Analog input 2 negative |
| ピン 6 | AVDD — Analog 3.3 V supply |
| ピン 7 | GND — Analog ground |
| ピン 8 | AINP3 — Analog input 3 positive |
| ピン 9 | AINM3 — Analog input 3 negative |
| ピン 10 | AINP4 — Analog input 4 positive |
| ピン 11 | AINM4 — Analog input 4 negative |
| ピン 12 | AVDD — Analog 3.3 V supply |
| ピン 13 | REFT — Internal reference top |
| ピン 14 | REFB — Internal reference bottom |
| ピン 15 | REFCM — Reference common-mode |
| ピン 16 | AVDD — Analog 3.3 V supply |
| ピン 17 | GND — Analog ground |
| ピン 18 | CLKP — Clock input positive |
| ピン 19 | CLKM — Clock input negative |
| ピン 20 | SCLK — Serial interface clock |
| ピン 21 | SDATA — Serial interface data |
| ピン 22 | SEN — Serial interface enable |
| ピン 23 | RESET — Hardware reset, active low |
| ピン 24 | PDN — Power down, active low |
| ピン 25 | DVDD — Digital 1.8 V supply |
| ピン 26 | GND — Digital ground |
| ピン 27 | LVDS_TEST — LVDS test mode enable |
| ピン 28 | GND — Digital ground |
| ピン 29 | DCLKOUTP — DDR clock output positive |
| ピン 30 | DCLKOUTM — DDR clock output negative |
| ピン 31 | DOUT8P — LVDS data output 8 positive |
| ピン 32 | DOUT8M — LVDS data output 8 negative |
| ピン 33 | DOUT7P — LVDS data output 7 positive |
| ピン 34 | DOUT7M — LVDS data output 7 negative |
| ピン 35 | DOUT6P — LVDS data output 6 positive |
| ピン 36 | DOUT6M — LVDS data output 6 negative |
| ピン 37 | DOUT5P — LVDS data output 5 positive |
| ピン 38 | DOUT5M — LVDS data output 5 negative |
| ピン 39 | DOUT4P — LVDS data output 4 positive |
| ピン 40 | DOUT4M — LVDS data output 4 negative |
| ピン 41 | DOUT3P — LVDS data output 3 positive |
| ピン 42 | DOUT3M — LVDS data output 3 negative |
| ピン 43 | DOUT2P — LVDS data output 2 positive |
| ピン 44 | DOUT2M — LVDS data output 2 negative |
| ピン 45 | DOUT1P — LVDS data output 1 positive |
| ピン 46 | DOUT1M — LVDS data output 1 negative |
| ピン 47 | DVDD — Digital 1.8 V supply |
| ピン 48 | GND — Digital ground |
| ピン 49 | AVDD — Analog 3.3 V supply |
| ピン 50 | GND — Analog ground |
| ピン 51 | AVDD — Analog 3.3 V supply |
| ピン 52 | FS_RANGE — Full-scale range select |
| ピン 53 | GAIN_EN — Per-channel gain adjust enable |
| ピン 54 | OFFSET_EN — Per-channel offset adjust enable |
| ピン 55 | LVDS_CNTL — LVDS control register select |
| ピン 56 | TEST1 — Test pin 1 (factory use) |
| ピン 57 | TEST2 — Test pin 2 (factory use) |
| ピン 58 | NC — Not connected (per datasheet) |
| ピン 59 | NC — Not connected (per datasheet) |
| ピン 60 | NC — Not connected (per datasheet) |
| ピン 61 | NC — Not connected (per datasheet) |
| ピン 62 | NC — Not connected (per datasheet) |
| ピン 63 | NC — Not connected (per datasheet) |
| ピン 64 | NC — Not connected (per datasheet) |
主な用途
ADS6425IRGCR の用途: 6 件s: Wireless Base Station Receiver, Medical Ultrasound Beamforming, Multi-Channel Data Acquisition System, Radar and Lidar Front-End, Test and Measurement Instrumentation, Communications Test Equipment.
Wireless Base Station Receiver
The ADS6425IRGCR is well-suited for wireless base station receivers where four simultaneous RF/IF channels must be digitized with tight channel-to-channel timing alignment. The 125 MSPS per-channel rate captures wide-bandwidth carriers while the 12-bit resolution supports >70 dB SNR for clean demodulation. Its serialized LVDS outputs minimize FPGA I/O pins, simplifying PCB routing in densely packed multi-antenna MIMO systems. The 3.3 V analog and 1.8 V digital supply rails align with typical base-station power architectures.
おすすめ
Medical Ultrasound Beamforming
In ultrasound beamformer front-ends, the ADS6425IRGCR provides 12-bit digitization at 125 MSPS across four channels, capturing return echoes from multiple transducer elements with low latency suitable for digital beamforming algorithms. The pipelined architecture adds only a few clock cycles of delay, preserving axial accuracy. The LVDS serialized interface allows many ADCs to share a common FPGA, scaling channel counts to 32, 64, or 128 elements without overwhelming the receiver.
おすすめ
Multi-Channel Data Acquisition System
For industrial data acquisition systems requiring simultaneous sampling of multiple sensor channels, the ADS6425IRGCR delivers 125 MSPS capture across four differential inputs, with the serialized LVDS output reducing FPGA pin count. The differential analog inputs reject common-mode noise from long sensor cables in factory automation environments. The exposed thermal pad of the VQFN-64 package enables reliable operation across the -40C to +85C industrial temperature range without external heatsinking.
おすすめ
Radar and Lidar Front-End
The ADS6425IRGCR fits radar and lidar front-end processing where four simultaneous IF or baseband channels must be sampled at high speed. The 125 MSPS rate captures wide-bandwidth chirp or pulse signals with adequate margin, and the 12-bit resolution preserves amplitude information needed for target detection. The pipelined architecture's deterministic latency simplifies range-bin calculations, while the LVDS interface preserves signal integrity over longer board traces to the FPGA processor.
おすすめ
Test and Measurement Instrumentation
In test and measurement instruments such as digital oscilloscopes and spectrum analyzers, the ADS6425IRGCR provides four-channel simultaneous sampling at 125 MSPS with 12-bit resolution. The serialized LVDS outputs reduce FPGA pin requirements, allowing more channels or higher-density processing. The internal clock stabilizer simplifies external PLL requirements, and the wide operating temperature range suits both laboratory and field-portable instruments.
おすすめ
Communications Test Equipment
The ADS6425IRGCR's combination of 125 MSPS sampling, four differential channels, and serialized LVDS outputs makes it suitable for communications test equipment measuring modulated signals. The 12-bit resolution captures EVM-sensitive constellations, and the simultaneous sampling maintains phase coherence across MIMO or multi-carrier test vectors. The 3.3 V AVDD plus 1.8 V DVDD rails integrate cleanly with FPGA-based signal processing platforms used in production test stations.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADS6425IRGCR — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS6425IRGCT | ADS6424IRGCR | ADS6424IRGCT | ADS6423IRGCR | ADS6422IRGCR | ADS6422IRGC25 |
|---|---|---|---|---|---|---|---|
| Package | VQFN-64 (RGC) 9x9 mm | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Sampling Rate | 125 MSPS | 125 MSPS | 105 MSPS | 105 MSPS | 80 MSPS | 65 MSPS | 65 MSPS |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Number of Channels | 4 differential | 4 differential | 4 differential | 4 differential | 4 differential | 4 differential | 4 differential |
| Data Output Interface | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS |
| Analog Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Pinout Compatibility | Reference | Identical | Identical | Identical | Identical | Identical | Identical |
主な差別化要因
- Highest sampling rate in the ADS642X quad-channel family （vs ADS6424IRGCR)
- Four differential channels with simultaneous sampling （vs ADS6422IRGCR)
- Serialized LVDS interface minimizes FPGA pin count （vs Parallel-output ADC families)
設計ノート
The ADS6425IRGCR requires a clean 3.3 V AVDD and 1.8 V DVDD supply; both rails should come from independent low-noise LDOs (such as TPS7A47xx family) rather than switching converters to preserve 12-bit SNR. Place 1 uF and 0.1 uF ceramic bypass capacitors close to each AVDD and DVDD pin pair, with a ferrite bead or RC filter between the analog and digital ground returns to break high-frequency ground loops that can couple into the analog inputs.
Route differential analog inputs (AINPx/AINMx) as length-matched 100 ohm differential pairs from the front-end driver or transformer to the ADC pins. Keep analog traces away from the LVDS data output pairs (DOUT1P/M through DOUT8P/M) and the DDR clock output (DCLKOUTP/M) to minimize digital-to-analog crosstalk. The exposed thermal pad (pin 65) must be soldered to a continuous ground plane with multiple vias for low theta-JA thermal dissipation.
Terminate each LVDS output pair (DOUTxP/DOUTxM) with a 100 ohm differential resistor placed within 1 cm of the FPGA receiver pins. Match trace lengths within each LVDS pair to within 0.5 mm to maintain differential balance, and avoid right-angle bends. The DDR clock output (DCLKOUTP/M) should be routed with controlled impedance and reference planes kept continuous to prevent reflections that would degrade timing margin at 125 MSPS.
Do not leave the input clock (CLKP/CLKM) floating; the ADS6425IRGCR requires a continuous differential LVDS or LVPECL clock to maintain stable sampling. Avoid driving the analog inputs beyond AVDD or below GND, as this will forward-bias the input ESD diodes and introduce nonlinearity. When using the internal reference, ensure REFT, REFB, and REFCM pins have proper 0.1 uF decoupling to AVSS to prevent reference instability at high input frequencies.
コンプライアンス情報
RoHS compliant per TI product page. Lead-free and halogen-free packaging. Industrial temperature grade -40C to +85C, not AEC-Q100 qualified for automotive applications. For automotive-qualified alternatives, see TI's automotive-grade ADC portfolio.
