LTC2192IUKG - 16-bit 65Msps Dual ADC | Analog Devices
部品番号: LTC2192IUKG ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $105.93 | $105.93 |
| 10 | $97.46 | $974.60 |
| 100 | $84.74 | $8,474.00 |
| 500 | $74.15 | $37,075.00 |
| 1,000 | $63.56 | $63,560.00 |
LTC2192IUKG 概要
An ADC (analog-to-digital converter) is a semiconductor device that converts continuous-time continuous-amplitude analog signals into discrete digital codes. Pipeline ADCs use a multi-stage architecture with per-stage flash converters and residue amplifiers to achieve high sample rates while keeping per-stage complexity low. Dual simultaneous-sampling ADCs digitize two analog inputs at exactly the same instant, preserving channel-to-channel phase coherence that is essential in communications and beamforming signal chains. The LTC2192 family sits within the broader ADC hierarchy: ADC -> data converter -> signal chain IC -> mixed-signal semiconductor.
Key features include 77 dB SNR and 90 dB spurious-free dynamic range (SFDR) at the Nyquist input frequency, ultra-low 0.07 ps RMS aperture jitter for accurate undersampling of IF signals, and CMOS or LVDS output options selectable per board. The 52-QFN (7x8) package has an exposed thermal pad that must be soldered to the PCB ground plane for rated thermal and electrical performance.
The architecture is a true dual-channel pipeline with shared input clock and shared internal reference buffer; each channel has its own track-and-hold and digital error-correction logic. The 0.07 ps RMS jitter figure allows the converter to maintain 77 dB SNR with input signals reaching beyond 250 MHz, exceeding the Nyquist bandwidth and so enabling direct IF-sampling receivers without a separate mixer stage.
Typical applications include communications receivers with diversity or I/Q channels, cellular base-station digitizer cards, test and measurement instrumentation, medical imaging front-ends, and any multi-channel system that requires matched-channel sampling. Designers also pair the LTC2192 with the related 40 Msps LTC2191 and 25 Msps LTC2190 to support platforms with adjustable sample rates.
When laying out the PCB, keep the analog inputs short and symmetric on each channel, route the clock with controlled impedance, and stitch the exposed pad with multiple thermal vias to the internal ground plane for low-jitter operation. Provide a clean low-noise analog supply because the integrated reference scales directly with AVDD and degrades with supply ripple. Decouple AVDD and DVDD with 1 µF and 0.1 µF ceramic capacitors placed within 5 mm of each supply pin.
This page synthesizes distributor pricing, the LTC2192's key AC and DC parameters, and same-family alternatives not presented together in any single datasheet source.
ドロップイン代替品: LTC2192IUKG — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2192IUKG （同一形状・フットプリント） — 相違点: RoHS Status, Resolution, SFDR, SNR, Input Type.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2192IUKG#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2192IUKG#TRPBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2192CUKG#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2191IUKG
✅ ドロップイン✓ 在庫あり
$62.95 / 個
データシートを見る →LTC2191CUKG
✅ ドロップイン✓ 在庫あり
$22.4 / 個
データシートを見る →LTC2190IUKG
✅ ドロップイン✓ 在庫あり
$18.21 / 個
データシートを見る →LTC2192IUKG 最大定格＆電気的特性
| 分解能 | 16 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate | 65 Msps |
| Architecture | Pipelined |
| Input Type | Differential (per channel) |
| SNR | 77 dB at Nyquist input (per datasheet) |
| SFDR | 90 dB (per datasheet) |
| Aperture Jitter | 0.07 ps RMS |
| Digital Output Interface | Parallel CMOS / Serial SPI / LVDS (selectable) |
| パッケージ | 52-pin QFN (7x8 mm) with exposed pad |
| 実装タイプ | Surface Mount |
| 動作温度範囲 | -40 C to +85 C (industrial, I-suffix) |
| RoHS ステータス | Compliant (per #PBF suffix) |
| Lead Finish | Lead-free (Pb-free) |
| Number of Inputs / Converter | 2 input, 2 pipelined ADCs |
LTC2192IUKG ピン構成
| ピン 1 | GND — Ground |
| ピン 2 | VAIN1+ — Channel A positive analog input |
| ピン 3 | VAIN1- — Channel A negative analog input |
| ピン 4 | GND — Ground |
| ピン 5 | REFH — Reference high pin, decouple with 2.2 uF to REFL |
| ピン 6 | REFL — Reference low pin (ground) |
| ピン 7 | GND — Ground |
| ピン 8 | VBIN1+ — Channel B positive analog input |
| ピン 9 | VBIN1- — Channel B negative analog input |
| ピン 10 | GND — Ground |
| ピン 11 | AVDD — Analog supply, decouple with 1 uF + 0.1 uF |
| ピン 12 | GND — Ground |
| ピン 13 | AVDD — Analog supply |
| ピン 14 | GND — Ground |
| ピン 15 | CLK+ — Positive clock input |
| ピン 16 | CLK- — Negative clock input (tie to GND if single-ended) |
| ピン 17 | GND — Ground |
| ピン 18 | OGND — Output driver ground |
| ピン 19 | OVDD — Output driver supply |
| ピン 20 | OGND — Output driver ground |
| ピン 21 | D0A — Channel A data bit 0 (LSB) / LVDS pair |
| ピン 22 | D1A — Channel A data bit 1 |
| ピン 23 | D2A — Channel A data bit 2 |
| ピン 24 | D3A — Channel A data bit 3 |
| ピン 25 | D4A — Channel A data bit 4 |
| ピン 26 | D5A — Channel A data bit 5 |
| ピン 27 | D6A — Channel A data bit 6 |
| ピン 28 | D7A — Channel A data bit 7 |
| ピン 29 | D8A — Channel A data bit 8 |
| ピン 30 | D9A — Channel A data bit 9 |
| ピン 31 | D10A — Channel A data bit 10 |
| ピン 32 | D11A — Channel A data bit 11 |
| ピン 33 | D12A — Channel A data bit 12 |
| ピン 34 | D13A — Channel A data bit 13 |
| ピン 35 | D14A — Channel A data bit 14 |
| ピン 36 | D15A — Channel A data bit 15 (MSB) |
| ピン 37 | OGND — Output driver ground |
| ピン 38 | OVDD — Output driver supply |
| ピン 39 | D0B — Channel B data bit 0 (LSB) |
| ピン 40 | D1B — Channel B data bit 1 |
| ピン 41 | D2B — Channel B data bit 2 |
| ピン 42 | D3B — Channel B data bit 3 |
| ピン 43 | D4B — Channel B data bit 4 |
| ピン 44 | D5B — Channel B data bit 5 |
| ピン 45 | D6B — Channel B data bit 6 |
| ピン 46 | D7B — Channel B data bit 7 |
| ピン 47 | D8B — Channel B data bit 8 |
| ピン 48 | D9B — Channel B data bit 9 |
| ピン 49 | D10B — Channel B data bit 10 |
| ピン 50 | D11B — Channel B data bit 11 |
| ピン 51 | D12B — Channel B data bit 12 |
| ピン 52 | GND — Ground / exposed pad connection |
主な用途
LTC2192IUKG の用途: 6 件s: Diversity Cellular Base-Station Receiver, I/Q Direct-Conversion Digitizer, Broadband Test and Measurement Instrumentation, Medical Ultrasound Imaging Front-End, Software-Defined Radio (SDR) Digitizer Card, Multi-Channel Industrial Data Acquisition.
Diversity Cellular Base-Station Receiver
The LTC2192IUKG's two simultaneous-sampling 16-bit channels at 65 Msps let a 4G/5G radio digitize two diversity antennas at the same instant, preserving phase coherence needed for combining. With 77 dB SNR and 90 dB SFDR per channel, the device sits between the analog IF filter and the digital baseband DSP, replacing the mixer-plus-IF-ADC chain. Designers typically run the part in LVDS DDR mode so the data buses stay noise-quiet at the radio board.
おすすめ
I/Q Direct-Conversion Digitizer
In an I/Q demodulator, the two ADC channels of the LTC2192IUKG capture the in-phase and quadrature paths simultaneously at 65 Msps, removing the skew that would otherwise corrupt image rejection. The 0.07 ps RMS aperture jitter keeps the SNR above 77 dB at high IF, allowing direct sampling of signals near 200 MHz. The 52-QFN (7x8) footprint and exposed pad make it practical for compact digitizer cards that bolt onto an FPGA-based demod board.
おすすめ
Broadband Test and Measurement Instrumentation
Test instruments benefit from the LTC2192IUKG's 77 dB SNR and 0.07 ps RMS jitter, which preserve measurement dynamic range on wideband stimulus signals. The two channels sample the device-under-test and a reference path at the same 65 Msps clock, supporting cross-correlation averaging that improves effective bits by approximately 3 dB per doubling of averages. The CMOS/LVDS-selectable output adapts the part to legacy parallel capture or modern FPGA-based acquisition cards.
おすすめ
Medical Ultrasound Imaging Front-End
Portable ultrasound carts deploy the LTC2192IUKG to digitize echo channels at 65 Msps with the 77 dB SNR needed to resolve 1 cm-deep tissue structures. The dual-channel design combines two receive beams per converter, halving board area versus single-channel parts. Low aperture jitter preserves axial resolution, while the exposed-pad 52-QFN (7x8) keeps the thermal footprint compatible with sealed handheld enclosures for point-of-care use.
おすすめ
Software-Defined Radio (SDR) Digitizer Card
The LTC2192IUKG's 65 Msps sample rate and 16-bit resolution offer envelope coverage up to approximately 30 MHz in real-sampling mode, suitable for direct HF/VHF SDR. Two simultaneous channels sample the I and Q rails, allowing software demodulation of AM, FM, SSB, and digital modes without an analog demodulator stage. The 52-QFN (7x8) package and CMOS/LVDS-selectable outputs interface cleanly to FPGA mezzanine cards and to host SDR software toolchains.
おすすめ
Multi-Channel Industrial Data Acquisition
Industrial DAQs pair the LTC2192IUKG with sensor-conditioning front-ends to digitize vibration, strain-gage, and accelerometer signals at 65 Msps per channel pair. The 77 dB SNR extends dynamic range on raw transducer outputs, while the simultaneous sampling preserves cross-channel correlation needed for modal analysis. The industrial -40 C to +85 C temperature rating supports deployment near motors, generators, and outdoor process equipment.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2192IUKG — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2192IUKG#PBF | LTC2192CUKG#PBF | LTC2191IUKG | LTC2190IUKG |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 52-QFN (7x8) | 52-QFN (7x8) - same | 52-QFN (7x8) - same | 52-QFN (7x8) - same | 52-QFN (7x8) - same |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit |
| Sample Rate | 65 Msps | 65 Msps | 65 Msps | 40 Msps | 25 Msps |
| Number of Channels | 2 (simultaneous) | 2 | 2 | 2 | 2 |
| Temperature Range | -40 C to +85 C (I-suffix) | -40 C to +85 C | 0 C to +70 C | -40 C to +85 C | -40 C to +85 C |
| Aperture Jitter | 0.07 ps RMS | 0.07 ps RMS | 0.07 ps RMS | 0.07 ps RMS | 0.07 ps RMS |
| SNR at Nyquist | 77 dB | 77 dB | 77 dB | 77 dB (at 40 Msps) | 77 dB (at 25 Msps) |
| Output Interface | CMOS/LVDS selectable | CMOS/LVDS selectable | CMOS/LVDS selectable | CMOS/LVDS selectable | CMOS/LVDS selectable |
主な差別化要因
- Dual simultaneous-sampling 16-bit channels at 65 Msps （vs LTC2162IUK)
- 77 dB SNR / 90 dB SFDR with 0.07 ps RMS jitter （vs LTC2156IUP-14)
- 52-pin QFN (7x8) with selectable CMOS/LVDS outputs （vs LTC2190IUKG)
- Industrial -40 C to +85 C temperature grade （vs LTC2192CUKG)
設計ノート
Route the two analog inputs VAIN1+/- and VBIN1+/- as symmetric 100-ohm differential pairs from the analog front-end to pins 2-3 and 8-9. Keep traces strictly matched in length to within 0.5 mm to preserve simultaneous-sampling phase coherence. Surround the analog input pins with a ground moat and stitch vias on a 1 mm pitch to suppress crosstalk between channel A and channel B inputs.
Decouple each AVDD pin (11, 13) with a 1 uF X7R ceramic in parallel with a 0.1 uF NP0 ceramic placed within 5 mm of the pin. Tie OVDD (pins 19, 38) to a separate digital 2.5 V or 3.3 V rail; never share this rail with the analog supply, because noise couples into the output drivers and degrades SNR. Place a ferrite bead between AVDD and the upstream LDO to attenuate switching noise.
Always solder the exposed pad to a continuous ground plane with at least eight thermal vias on a 1.2 mm pitch. Skipping the pad soldering causes the internal reference to drift, aperture jitter to rise, and the part to fail under thermal cycling. The pad is the primary heat path and the AC ground reference for the input track-and-hold; floating it degrades all AC specifications.
Drive CLK+ and CLK- from a low-jitter clock source (e.g., a TCXO or a jitter-attenuating PLL) with 50-ohm termination to a clean bias voltage. A 1 ps RMS degradation in clock jitter directly subtracts from SNR, so a noisy FPGA PLL is not suitable in high-frequency IF sampling designs. If single-ended clocking is unavoidable, tie CLK- to GND through 50 ohms and AC-couple CLK+ with a 1 nF capacitor.
コンプライアンス情報
RoHS and lead-free compliance indicated by #PBF and #TRPBF ordering suffixes per Analog Devices' standard Pb-free part-numbering convention. AEC-Q100 not applicable for this industrial-temp grade dual ADC.
