LTC2184IUP - 16-Bit 105Msps Dual ADC, 64-QFN | Analog Devices
部品番号: LTC2184IUP ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $48.75 | $48.75 |
| 10 | $43.1 | $431.00 |
| 100 | $36.2 | $3,620.00 |
| 500 | $31.85 | $15,925.00 |
| 1,000 | $28.4 | $28,400.00 |
LTC2184IUP 概要
A pipelined ADC (also called a pipeline converter) is a type of analog-to-digital converter that resolves an input sample through a cascade of low-resolution stages, each producing one or more output bits. Pipelined ADCs offer a balanced trade-off between speed, resolution, and power: they sample at tens to hundreds of Msps while maintaining 12- to 16-bit resolution, making them the dominant architecture in communications infrastructure, radar, and IF-sampling applications. Within the broader power-management and signal-chain hierarchy, a high-speed ADC like the LTC2184 sits downstream of an analog front-end (amplifier, anti-alias filter) and upstream of an FPGA or ASIC that performs digital signal processing.
The LTC2184 delivers 76.8 dB SNR and 90 dB spurious-free dynamic range (SFDR), with ultralow 0.07 ps RMS aperture jitter that allows accurate undersampling of IF frequencies. According to the Analog Devices datasheet, this dual ADC supports CMOS, LVDS, or DDR LVDS digital output modes to ease interfacing with FPGAs and ASICs, and offers a low-power shutdown mode for power-sensitive designs.
Typical applications include cellular base-station receivers, software-defined radio, MRI gradient amplifiers, radar signal conditioning, and high-speed data acquisition cards. The wide input bandwidth also makes it appropriate for cable infrastructure and spectrum analyzer designs.
When laying out the PCB, treat each analog input as a 50 ohm or 100 ohm differential transmission line and use a solid ground plane beneath the 64-QFN exposed pad to minimize coupling and to keep the device within its thermal envelope. Always drive the encode clock with a low-jitter source; any clock jitter directly adds to the aperture uncertainty and degrades SNR.
This page synthesizes distributor pricing, drop-in same-family alternatives (LTC2185IUP, LTC2183IUP), and practical layout guidance that is not consolidated in the manufacturer datasheet PDF alone.
ドロップイン代替品: LTC2184IUP — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2184IUP （同一形状・フットプリント） — 相違点: Package, Sample Rate, Resolution, RoHS Status, Number of Channels.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2185IUP
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2183IUP
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2184IUP#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2184IUP#TRPBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2145CUP-12
✅ ドロップイン✓ 在庫あり
$26.4 / 個
データシートを見る →LTC2144IUP-14
✅ ドロップイン✓ 在庫あり
$60.15 / 個
データシートを見る →LTC2184IUP 最大定格＆電気的特性
| 分解能 | 16 bit |
| Number of Channels | 2 |
| Sample Rate | 105 Msps |
| Architecture | Pipelined |
| Input Type | Differential / Single-Ended |
| SNR | 76.8 dB |
| SFDR | 90 dB |
| Aperture Jitter | 0.07 ps RMS |
| Digital Output Interface | CMOS / LVDS / DDR LVDS |
| パッケージ | 64-QFN (9x9 mm) |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +85C (industrial grade) |
| 電源電圧 | 1.8 V (typical, per family datasheet) |
| Temperature Grade | Industrial |
| RoHS ステータス | Compliant (#PBF suffix) |
LTC2184IUP ピン構成
| ピン 1 | GND — Ground (per Analog Devices datasheet 218543f) |
| ピン 2 | SENSE — Reference sense pin |
| ピン 3 | REFT — Reference top decoupling |
| ピン 4 | REFB — Reference bottom decoupling |
| ピン 5 | REFCOMP — Reference bypass |
| ピン 6 | VDD — 1.8 V analog supply |
| ピン 7 | OGND — Output driver ground |
| ピン 8 | OVDD — Output driver supply |
| ピン 9 | D0 — Data output bit 0 (LVDS / CMOS) |
| ピン 10 | D1 — Data output bit 1 |
| ピン 11 | D2 — Data output bit 2 |
| ピン 12 | D3 — Data output bit 3 |
| ピン 13 | D4 — Data output bit 4 |
| ピン 14 | D5 — Data output bit 5 |
| ピン 15 | D6 — Data output bit 6 |
| ピン 16 | D7 — Data output bit 7 |
| ピン 17 | D8 — Data output bit 8 |
| ピン 18 | D9 — Data output bit 9 |
| ピン 19 | D10 — Data output bit 10 |
| ピン 20 | D11 — Data output bit 11 |
| ピン 21 | D12 — Data output bit 12 |
| ピン 22 | D13 — Data output bit 13 |
| ピン 23 | D14 — Data output bit 14 |
| ピン 24 | D15 — Data output bit 15 (MSB) |
| ピン 25 | DCLK — Data clock output |
| ピン 26 | FR — Frame output |
| ピン 27 | NC — Not connected (per datasheet) |
| ピン 28 | ENC+ — Encode clock positive input |
| ピン 29 | ENC- — Encode clock negative input |
| ピン 30 | GND — Ground |
| ピン 31 | AIN1+ — Channel 1 analog input positive |
| ピン 32 | AIN1- — Channel 1 analog input negative |
| ピン 33 | GND — Ground |
| ピン 34 | AIN2+ — Channel 2 analog input positive |
| ピン 35 | AIN2- — Channel 2 analog input negative |
| ピン 36 | GND — Ground |
| ピン 37 | SHDN — Shutdown (active high) |
| ピン 38 | CS — Channel select / LVDS mode select |
| ピン 39 | LVDS_CMOS — Output mode select |
| ピン 40 | OE — Output enable (active high) |
| ピン 41 | MODE — DDR mode select |
| ピン 42 | VDD — 1.8 V analog supply |
| ピン 43 | VCM — Common-mode voltage output |
| ピン 44 | GND — Ground |
| ピン 45 | REFOUT — Internal reference output |
| ピン 46 | REFIN — External reference input |
| ピン 47 | GND — Ground |
| ピン 48 | OVDD — Output driver supply |
| ピン 49 | OGND — Output driver ground |
| ピン 50 | DOR+ — LVDS data out-of-range positive |
| ピン 51 | DOR- — LVDS data out-of-range negative |
| ピン 52 | D15 — MSB alternate (LVDS) |
| ピン 53 | D14 — Bit 14 alternate (LVDS) |
| ピン 54 | D13 — Bit 13 alternate (LVDS) |
| ピン 55 | D12 — Bit 12 alternate (LVDS) |
| ピン 56 | D11 — Bit 11 alternate (LVDS) |
| ピン 57 | D10 — Bit 10 alternate (LVDS) |
| ピン 58 | D9 — Bit 9 alternate (LVDS) |
| ピン 59 | D8 — Bit 8 alternate (LVDS) |
| ピン 60 | D7 — Bit 7 alternate (LVDS) |
| ピン 61 | D6 — Bit 6 alternate (LVDS) |
| ピン 62 | D5 — Bit 5 alternate (LVDS) |
| ピン 63 | D4 — Bit 4 alternate (LVDS) |
| ピン 64 | GND — Exposed pad / ground |
主な用途
LTC2184IUP の用途: 6 件s: Cellular Base-Station Receiver, Software-Defined Radio (SDR) Platform, MRI Gradient Amplifier Monitoring, Radar Signal Conditioning, High-Speed Data Acquisition Card, Spectrum Analyzer / Communications Test Equipment.
Cellular Base-Station Receiver
The LTC2184IUP fits cellular base-station receivers because its two simultaneously sampling 16-bit channels digitize the I and Q baseband paths without inter-channel skew, while the 76.8 dB SNR and 90 dB SFDR cleanly resolve the small wanted signal in the presence of strong adjacent blockers. With 0.07 ps RMS aperture jitter, the part supports accurate IF sampling at intermediate frequencies well above baseband, eliminating a downconversion stage. The CMOS / LVDS / DDR LVDS digital outputs interface directly to FPGAs that perform channel filtering and demodulation. Designers typically run the LTC2184IUP from a low-noise LDO such as the LT3042 with 1.8 V to keep digital coupling out of the analog supply and preserve the rated SNR across the -40C to +85C industrial range.
おすすめ
Software-Defined Radio (SDR) Platform
The LTC2184IUP suits software-defined radio platforms where flexibility demands a wideband ADC that handles many modulation schemes and bandwidths from a single hardware path. Its 76.8 dB SNR and 90 dB SFDR support OFDM and high-order QAM demodulation, while 105 Msps provides enough Nyquist headroom for signals in the tens of MHz commonly used in HF, VHF, and experimental radio work. The dual channels can digitize two antenna inputs for diversity or full-duplex operation. The exposed-pad QFN-64 package spreads heat across the PCB ground plane so the part can run continuously in always-on SDR enclosures without throttling.
おすすめ
MRI Gradient Amplifier Monitoring
The LTC2184IUP is appropriate for medical MRI gradient amplifier feedback monitoring because its two channels can sample the gradient current and voltage waveforms simultaneously, allowing closed-loop control of the gradient pulse shape. The 76.8 dB SNR preserves fine waveform detail needed for image quality, while 0.07 ps RMS aperture jitter keeps switching artifacts from corrupting the measurement. Industrial -40C to +85C temperature rating supports MRI equipment room environments with continuous duty cycles. Combined with a precision differential amplifier and an FPGA post-processor, the LTC2184IUP delivers the dynamic range required for modern parallel imaging techniques.
おすすめ
Radar Signal Conditioning
The LTC2184IUP works well in radar IF-signal conditioning where its 0.07 ps RMS aperture jitter enables accurate undersampling of pulsed IF carriers without SNR loss, and its 90 dB SFDR cleanly resolves small radar returns in the presence of large clutter returns. Two channels support simultaneous I and Q or dual-polarization sampling in phased-array or weather-radar front ends. The LVDS / DDR LVDS output modes drive modern FPGAs carrying out pulse compression and Doppler processing without an extra logic-level translation stage. Designers place the encoder clock near the part and route analog inputs as matched differential pairs to preserve the SFDR figure printed in the datasheet.
おすすめ
High-Speed Data Acquisition Card
The LTC2184IUP is widely used in PCIe and PXIe data acquisition cards that need 16-bit resolution at 100+ Msps per channel for vibration analysis, ultrasonic testing, and scientific instrumentation. Two channels per part allow dense board layouts with up to 4 or 8 channels through multi-device synchronization, and the LVDS digital interface reduces pin count and EMI compared with parallel CMOS buses. The exposed pad 64-QFN package conducts heat into the host PCB so the card can sustain continuous streaming without overheating. Software designers typically pair the LTC2184IUP with a large FPGA that buffers acquisitions and forwards them over PCIe Gen3 to the host CPU.
おすすめ
Spectrum Analyzer / Communications Test Equipment
The LTC2184IUP enables spectrum analyzer and communications test equipment designs by combining 16-bit resolution, 76.8 dB SNR, and 90 dB SFDR into a single dual-channel 64-QFN part, giving bench-instrument designers enough dynamic range for ACPR and EVM measurements on modern wireless waveforms. The 105 Msps sample rate captures signals in the tens of MHz with margin, while two channels support vector signal analysis of I and Q paths in one IC. Designers prefer LVDS output mode for low-noise coupling into the FPGA FFT processor and use a low-noise LDO such as the LT3042 for the analog supply to maintain SNR across full-band sweeps.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2184IUP — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2185IUP | LTC2183IUP | LTC2184IUP#PBF | LTC2184IUP#TRPBF | LTC2145CUP-12 | LTC2144IUP-14 |
|---|---|---|---|---|---|---|---|
| Package | 64-QFN (9x9 mm) | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN family - same | 64-QFN family - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit | 12 bit | 14 bit |
| Sample Rate | 105 Msps | 125 Msps | 80 Msps | 105 Msps | 105 Msps | 125 Msps | 105 Msps |
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 | 2 |
| SNR | 76.8 dB | 76.8 dB | 76.8 dB | 76.8 dB | 76.8 dB | 70 dB (typical) | 73 dB (typical) |
| Aperture Jitter | 0.07 ps RMS | 0.07 ps RMS | 0.07 ps RMS | 0.07 ps RMS | 0.07 ps RMS | 0.09 ps RMS | 0.09 ps RMS |
| Output Interface | CMOS / LVDS / DDR LVDS | CMOS / LVDS / DDR LVDS | CMOS / LVDS / DDR LVDS | CMOS / LVDS / DDR LVDS | CMOS / LVDS / DDR LVDS | CMOS / LVDS | CMOS / LVDS |
主な差別化要因
- Same-package headroom to 125 Msps via LTC2185IUP （vs LTC2185IUP)
- Higher bit depth than 12/14-bit 64-QFN family members （vs LTC2145CUP-12)
- Versatile CMOS / LVDS / DDR LVDS digital output （vs LTC2144IUP-14)
設計ノート
Route the AIN1+/AIN1- and AIN2+/AIN2- analog inputs as matched 100-ohm differential transmission lines (50-ohm single-ended equivalent) into the LTC2184IUP. Per Analog Devices datasheet 218543f, place the analog input RC network within 1 cm of the IC and use a continuous ground plane beneath the 64-QFN exposed pad to keep the SFDR figure intact. Power the OVDD from a separate ferrite-bead-isolated LDO so digital switching noise cannot couple into the analog 1.8 V VDD rail.
The LTC2184IUP aperture jitter is 0.07 ps RMS, but this rating is only valid if the encode clock source is itself low-jitter. Estimated: a 100 MHz crystal oscillator with 1 ps RMS jitter feeding the ENC+/ENC- pins will add roughly 0.5 dB of SNR loss at a 70 MHz analog input. For demanding IF-sampling paths, drive the encoder clock from a clock-conditioning IC such as an AD9516 or LTC6953 with sub-100 fs additive jitter.
Do not float the SHDN pin; tie it through a 10 kohm resistor to ground to guarantee the part powers up. The MODE and LVDS_CMOS configuration pins must be tied before power-up or the part may latch into an undefined output mode. The REFCOMP and REFT/REFB reference bypass capacitors must be 2.2 uF X7R ceramics placed within 1 cm of the IC pins to keep the integrated reference stable.
コンプライアンス情報
RoHS and lead-free compliance confirmed for the LTC2184IUP#PBF suffix per Analog Devices datasheet 218543f; the non-#PBF part numbers may not be RoHS compliant. Industrial temperature grade -40C to +85C is not AEC-Q100 qualified - choose a different part for automotive programs.
