LTC2222IUK-11 - 11-Bit 105Msps ADC | Analog Devices
部品番号: LTC2222IUK-11 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $29.85 | $2,985.00 |
| 500 | $25.4 | $12,700.00 |
| 1,000 | $21.75 | $21,750.00 |
LTC2222IUK-11 概要
An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog signals into discrete digital codes at a specified sampling rate, serving as the bridge between the analog front-end (amplifiers, filters, transducers) and the digital signal processor, FPGA, or microcontroller. The pipelined ADC architecture used in the LTC2222IUK-11 enables high sampling rates with low power by processing each sample through a cascade of low-resolution stages, balancing speed, resolution, and die area efficiently. Within the signal-chain hierarchy, the ADC sits after the anti-alias filter and before the digital decimator or processor.
Key features include 65.4 dB SNR and 80 dB SFDR for input frequencies up to 150 MHz, selectable ±0.5 V or ±1 V input ranges, no missing codes over temperature, optional clock duty-cycle stabilizer, and shutdown/nap modes for power management. The integrated sample-and-hold amplifier and CMOS-compatible outputs simplify interface to FPGAs and ASICs.
The pipelined architecture of the LTC2222IUK-11 uses multi-bit per-stage conversion with digital error correction, achieving low spurious content and high linearity while operating at 105 Msps. The clock duty-cycle stabilizer relaxes the timing requirement on the external encode clock source, allowing use of lower-cost oscillators without degrading AC performance.
Typical applications include wideband communications receivers, IF sampling in software-defined radio, cable head-end equipment, digital oscilloscopes, and medical imaging front-ends. The wide input bandwidth makes it suitable for undersampling IF architectures in cellular base-station designs. A key design consideration is providing a low-jitter encode clock and proper RF layout around the analog inputs to achieve the rated SNR; thermal management of the exposed pad is also important at full sampling rate.
ドロップイン代替品: LTC2222IUK-11 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2222IUK-11 （同一形状・フットプリント） — 相違点: Package, Power Dissipation, Resolution, RoHS Status, Supply Voltage.
クイック比較ツール — 並列比較する代替部品を選択:
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LTC2222IUK-11 最大定格＆電気的特性
| 分解能 | 11 bits (12-bit ADC family) |
| Sample Rate | 105 Msps |
| Number of Input Channels | 1 |
| Architecture | Pipelined |
| Input Bandwidth (Full Power) | 775 MHz |
| Signal-to-Noise Ratio (SNR) | 65.4 dB at 140 MHz input |
| Spurious-Free Dynamic Range (SFDR) | 80 dB at 150 MHz input |
| 入力電圧範囲 | Selectable ±0.5 V or ±1 V |
| 電源電圧 | Single 3.3 V |
| Power Dissipation | 475 mW (typical at 105 Msps) |
| Missing Codes | None (guaranteed) |
| Output Format | CMOS |
| 動作温度範囲 | -40C to +85C (industrial, I grade) |
| パッケージ | 48-QFN (7x7 mm, UK package) - MO-220-WKKD-2 |
| 実装タイプ | Surface Mount |
| Clock Duty Cycle Stabilizer | Yes (optional) |
| Shutdown / Nap Modes | Yes |
| Data Ready Output | Yes |
| RoHS ステータス | Compliant (PBF suffix) |
| Lead-Free | Yes (PBF suffix) |
LTC2222IUK-11 ピン構成
| ピン 1 | AIN+ — Differential analog input positive |
| ピン 2 | AIN- — Differential analog input negative |
| ピン 3 | SENSE — Reference mode select (internal/external) |
| ピン 4 | VREF — Reference voltage bypass |
| ピン 5 | REFT — Top reference decoupling |
| ピン 6 | REFB — Bottom reference decoupling |
| ピン 7 | REFCM — Common-mode reference |
| ピン 8 | VDD — Analog 3.3 V supply |
| ピン 9 | GND — Analog ground |
| ピン 10 | ENC+ — Encode clock positive |
| ピン 11 | ENC- — Encode clock complement |
| ピン 12 | GND — Clock ground |
| ピン 13 | CS — Chip select (active low) |
| ピン 14 | SHUTDN |
| ピン 15 | NAP — Nap mode (active low) |
| ピン 16 | OGND — Output driver ground |
| ピン 17 | OVDD — Output driver supply |
| ピン 18 | D11 |
| ピン 19 | D10 — Data output bit 10 |
| ピン 20 | D9 — Data output bit 9 |
| ピン 21 | D8 — Data output bit 8 |
| ピン 22 | D7 — Data output bit 7 |
| ピン 23 | D6 — Data output bit 6 |
| ピン 24 | D5 — Data output bit 5 |
| ピン 25 | D4 — Data output bit 4 |
| ピン 26 | D3 — Data output bit 3 |
| ピン 27 | D2 — Data output bit 2 |
| ピン 28 | D1 — Data output bit 1 |
| ピン 29 | D0 — LSB data output |
| ピン 30 | NC — Not connected |
| ピン 31 | OGND — Output driver ground |
| ピン 32 | OVDD — Output driver supply |
| ピン 33 | DR — Data ready output |
| ピン 34 | NC — Not connected |
| ピン 35 | NC — Not connected |
| ピン 36 | NC — Not connected |
| ピン 37 | OF — Output format select |
| ピン 38 | RAND — Randomizer enable |
| ピン 39 | DITH — Dither enable |
| ピン 40 | MODE — Clock duty cycle stabilizer mode |
| ピン 41 | GND — Analog ground |
| ピン 42 | VDD — Analog 3.3 V supply |
| ピン 43 | NC — Not connected |
| ピン 44 | NC — Not connected |
| ピン 45 | NC — Not connected |
| ピン 46 | NC — Not connected |
| ピン 47 | NC — Not connected |
| ピン 48 | NC — Not connected |
主な用途
LTC2222IUK-11 の用途: 6 件s: Wideband Communications Receiver IF Sampling, Software-Defined Radio (SDR) Front-End, Cable Head-End Downstream Capture, Digital Oscilloscope and Data Acquisition, Medical Imaging Front-End (Ultrasound / Beamforming), Radar and Lidar Signal Processing.
Wideband Communications Receiver IF Sampling
The LTC2222IUK-11 suits wideband communications receiver IF sampling where the 775 MHz full-power input bandwidth and 105 Msps sample rate allow direct undersampling of IF carriers at 70-140 MHz without an external mixer-to-baseband stage. The 65.4 dB SNR and 80 dB SFDR preserve signal fidelity for demodulation of multi-carrier signals. Power consumption of 475 mW from a single 3.3 V supply simplifies thermal design in densely populated line-card PCBs. Clock duty-cycle stabilizer relaxes timing constraints when generating the encode clock from a low-cost PLL.
おすすめ
Software-Defined Radio (SDR) Front-End
Software-defined radio platforms benefit from the LTC2222IUK-11's wide analog input bandwidth, which captures large spectrum slices and pushes digitization closer to the antenna. The 11-bit resolution is sufficient for many narrowband demodulation schemes, while the CMOS outputs stream directly into an FPGA for real-time DDC processing. Selectable ±0.5 V or ±1 V input ranges accommodate different front-end LNA gain settings. Nap and shutdown modes enable duty-cycled battery operation in portable SDR gear.
おすすめ
Cable Head-End Downstream Capture
Cable head-end downstream capture digitizes the full DOCSIS downstream spectrum (54-1002 MHz) using high-IF sampling ADCs like the LTC2222IUK-11. The 775 MHz analog input bandwidth covers the highest downstream block, while the pipelined architecture delivers clean SNR for QAM demodulation. Single 3.3 V supply operation simplifies the rack-mount power architecture. Shutdown modes support redundant-path failover schemes common in head-end CMTS equipment.
おすすめ
Digital Oscilloscope and Data Acquisition
The LTC2222IUK-11 fits into mainstream digital oscilloscope and data acquisition front-ends where the 105 Msps rate and 775 MHz full-power bandwidth deliver real-time digitizing of repetitive and single-shot signals up to Nyquist. The 65.4 dB SNR supports 11 effective bits suitable for general-purpose measurement. Pin compatibility with the LTC2222 (12-bit) and LTC2223 (80 Msps) family lets OEMs flex resolution/speed without PCB rework, reducing SKU complexity.
おすすめ
Medical Imaging Front-End (Ultrasound / Beamforming)
Ultrasound and beamforming front-ends benefit from the LTC2222IUK-11's low power (475 mW) per channel, which keeps thermal load manageable when many channels are tiled across a probe. The 105 Msps sample rate matches typical RF ultrasound bandwidth (up to 40 MHz), and the 11-bit resolution is adequate for harmonic detection when paired with time-gain compensation. CMOS outputs interface directly to FPGA-based beamforming pipelines.
おすすめ
Radar and Lidar Signal Processing
Radar and lidar baseband signal chains benefit from the LTC2222IUK-11's combination of high sample rate, wide input bandwidth, and selectable input range. The 775 MHz bandwidth captures wideband chirp returns, and 11-bit resolution is sufficient for detecting closely spaced targets after matched filtering. Low-jitter encode clock requirements are relaxed by the integrated duty-cycle stabilizer, allowing use of standard CMOS clock sources.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2222IUK-11 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2222IUK | LTC2223IUK | LTC2232IUK | LTC2233IUK |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 48-QFN (7x7 mm, UK) | 48-QFN (7x7 mm, UK) | 48-QFN (7x7 mm, UK) | 48-QFN (7x7 mm, UK) | 48-QFN (7x7 mm, UK) |
| Resolution | 11 bits | 12 bits | 12 bits | 10 bits | 10 bits |
| Sample Rate | 105 Msps | 105 Msps | 80 Msps | 105 Msps | 80 Msps |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
主な差別化要因
- Wide 775 MHz analog input bandwidth for IF undersampling （vs LTC2233IUK (10-bit, 80 Msps))
- 11-bit resolution optimized for high-IF communications （vs LTC2222IUK (12-bit, 105 Msps))
- Pin-compatible family spans 80-135 Msps and 10/11/12-bit resolution （vs Standalone fixed-resolution ADC)
設計ノート
Differential analog inputs (AIN+, AIN-) must be routed as a tightly-coupled differential trace (100 ohm differential impedance) with matched lengths to preserve SNR and SFDR at high input frequencies. Keep analog traces away from digital output lines and clock traces. Use a continuous ground plane on layer 2 directly beneath the analog input traces to minimize return-path discontinuities per Analog Devices evaluation board layout guidelines.
The exposed pad on the bottom of the 48-QFN package must be soldered to a ground copper pour with an array of thermal vias (typically 9-12 vias in a 3x3 grid) to achieve the specified thermal resistance. At 475 mW dissipation, the junction-to-ambient thermal resistance of the UK package (approximately 30 C/W with proper layout) limits the maximum ambient temperature to roughly 70 C at full sample rate before derating.
Decouple each VDD pin with a 0.1 uF ceramic capacitor placed within 3 mm of the pin, plus a 10 uF bulk capacitor near the analog supply pin. Keep digital OVDD and analog VDD supplies separate until they join at the regulator output; this prevents digital switching noise from coupling into the analog supply rail and degrading SNR.
Use a low-jitter encode clock source (< 1 ps RMS jitter) to achieve the rated SNR. The optional clock duty-cycle stabilizer (MODE pin) compensates for clock duty-cycle error but does not fix poor jitter performance. Verify that the encode clock signal meets the minimum amplitude specification (1V p-p differential) at the ENC+/ENC- pins at the full 105 MHz sample rate.
コンプライアンス情報
RoHS and lead-free compliance confirmed by PBF suffix per Analog Devices ordering information. AEC-Q100 qualification status not stated in the provided web data. Halogen-free status not stated in the provided data.
