LTC2240IUP-10 - 10-Bit 170Msps ADC, 64-QFN | Analog Devices
部品番号: LTC2240IUP-10 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $26.2 | $262.00 |
| 100 | $23.4 | $2,340.00 |
| 500 | $20.95 | $10,475.00 |
| 1,000 | $18.75 | $18,750.00 |
LTC2240IUP-10 概要
What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed ADC architecture that processes the analog input through a cascade of low-resolution flash stages, each handling a subset of the bits and feeding a residue to the next stage. This parallelism allows sample rates from tens of MSPS to several hundred MSPS with low power consumption and high dynamic range, sitting at the top of the speed hierarchy below flash ADCs but above successive-approximation (SAR) and delta-sigma converters. Pipelined ADCs are the workhorse of communications infrastructure, radar, test equipment, and digital oscilloscopes.
Key specifications of the LTC2240IUP-10 include a 170 Msps maximum sample rate, 10-bit resolution, 1.4 GHz analog input bandwidth, single 3V supply operation (2.85V to 3.4V), and LVDS or CMOS compatible digital outputs. The device integrates an internal sample-and-hold, programmable gain amplifier, and internal reference, simplifying board-level design and reducing external component count.
The architecture uses a multi-stage pipelined core with digital error correction, achieving low latency and excellent spurious-free dynamic range (SFDR) for narrowband and wideband inputs alike. Differential clock inputs and flexible output clocking allow easy interface to FPGAs and dedicated clock-generation ICs.
Typical applications include cellular basestation receivers, cable head-end equipment, medical imaging, radar IF digitizers, and high-speed data acquisition. The wide analog input bandwidth also makes the part suitable for direct-IF sampling in software-defined radio (SDR) designs.
A key design consideration is the clock jitter budget. Because SNR degrades with aperture uncertainty at high input frequencies, pair the LTC2240IUP-10 with a low-jitter clock source (sub-200 fs rms) and follow standard high-speed ADC layout practices with a solid ground plane and properly bypassed analog/digital domains.
This page synthesizes distributor pricing from DigiKey and Mouser, drop-in LTC22xx family alternatives already on XAIPART, and practical design notes not consolidated in the manufacturer datasheet.
ドロップイン代替品: LTC2240IUP-10 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2240IUP-10 （同一形状・フットプリント） — 相違点: SNR, SFDR, Package, Sample Rate, Resolution.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2184IUP
✅ ドロップイン✓ 在庫あり
$28.4 / 個
データシートを見る →LTC2156IUP-14
✅ ドロップイン✓ 在庫あり
$134.1 / 個
データシートを見る →LTC2221CUP
✅ ドロップイン✓ 在庫あり
$34.2 / 個
データシートを見る →LTC2145CUP-12
✅ ドロップイン✓ 在庫あり
$26.4 / 個
データシートを見る →LTC2122CUK
✅ ドロップイン✓ 在庫あり
$83 / 個
データシートを見る →LTC2240IUP-10 最大定格＆電気的特性
| 分解能 | 10 bit |
| Sample Rate | 170 Msps |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Input Bandwidth | 1.4 GHz |
| SNR | 60.6 dB |
| SFDR | 80 dB |
| 電源電圧 | 2.85 V to 3.4 V (single 3 V) |
| Digital Output Interface | LVDS / CMOS selectable |
| Analog Input Type | Differential |
| パッケージ | 64-QFN (UP, 9x9 mm) |
| ピン数 | 64 |
| Temperature Grade | Industrial (-40C to +85C) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant (#PBF suffix) |
LTC2240IUP-10 ピン構成
| ピン 1 | AIN+ — Differential analog input (positive) |
| ピン 2 | AIN- — Differential analog input (negative) |
| ピン 3 | GND — Ground |
| ピン 4 | VCM — Common-mode voltage output |
| ピン 5 | VREF — Reference voltage decoupling |
| ピン 6 | SENSE — Reference sense pin |
| ピン 7 | VCC — 3V analog supply |
| ピン 8 | GND — Ground |
| ピン 9 | OGND — Output driver ground |
| ピン 10 | OVCC — Output driver supply |
| ピン 11 | D0 — Data output bit 0 (LSB) |
| ピン 12 | D1 — Data output bit 1 |
| ピン 13 | D2 — Data output bit 2 |
| ピン 14 | D3 — Data output bit 3 |
| ピン 15 | D4 — Data output bit 4 |
| ピン 16 | D5 — Data output bit 5 |
| ピン 17 | D6 — Data output bit 6 |
| ピン 18 | D7 — Data output bit 7 |
| ピン 19 | D8 — Data output bit 8 |
| ピン 20 | D9 — Data output bit 9 (MSB) |
| ピン 21 | DNR — Data not ready / output clock auxiliary |
| ピン 22 | OF — Output format select (LVDS/CMOS) |
| ピン 23 | MODE — Operating mode select |
| ピン 24 | OGND — Output driver ground |
| ピン 25 | OVCC — Output driver supply |
| ピン 26 | DCO — Data clock output (LVDS) |
| ピン 27 | FR — Frame output |
| ピン 28 | GND — Ground |
| ピン 29 | NC — Not connected (per datasheet) |
| ピン 30 | NC — Not connected (per datasheet) |
| ピン 31 | CLK+ — Differential clock input (positive) |
| ピン 32 | CLK- — Differential clock input (negative) |
| ピン 33 | GND — Ground |
| ピン 34 | ENC+ — Encoded clock (positive) |
| ピン 35 | ENC- — Encoded clock (negative) |
| ピン 36 | VCC — 3V analog supply |
| ピン 37 | GND — Ground |
| ピン 38 | SHDN — Shutdown (active high) |
| ピン 39 | PGA — Programmable gain amplifier control |
| ピン 40 | VCM — Common-mode voltage bypass |
| ピン 41 | VREF — Reference decoupling |
| ピン 42 | GND — Ground |
| ピン 43 | VCC — 3V analog supply |
| ピン 44 | NC — Not connected (per datasheet) |
| ピン 45 | NC — Not connected (per datasheet) |
| ピン 46 | AIN+ — Differential analog input (positive, alternate) |
| ピン 47 | AIN- — Differential analog input (negative, alternate) |
| ピン 48 | GND — Ground |
| ピン 49 | VCC — 3V analog supply |
| ピン 50 | OGND — Output driver ground |
| ピン 51 | OVCC — Output driver supply |
| ピン 52 | DCO+ — Data clock output (LVDS positive) |
| ピン 53 | DCO- — Data clock output (LVDS negative) |
| ピン 54 | FR+ — Frame output (LVDS positive) |
| ピン 55 | FR- — Frame output (LVDS negative) |
| ピン 56 | D0+ — LVDS data bit 0 positive |
| ピン 57 | D0- — LVDS data bit 0 negative |
| ピン 58 | D1+ — LVDS data bit 1 positive |
| ピン 59 | D1- — LVDS data bit 1 negative |
| ピン 60 | OGND — Output driver ground |
| ピン 61 | OVCC — Output driver supply |
| ピン 62 | TEST1 — Factory test pin (tie to ground in application) |
| ピン 63 | TEST2 — Factory test pin (tie to ground in application) |
| ピン 64 | GND — Ground (exposed pad also bonded to GND) |
主な用途
LTC2240IUP-10 の用途: 7 件s: Cellular Basestation Receiver, Cable Head-End QAM Demodulator, Radar IF Digitizer, Software-Defined Radio IF Sampling, Medical Imaging Front-End, High-Speed Data Acquisition Card, Spectrum Analyzer IF Digitizer.
Cellular Basestation Receiver
The LTC2240IUP-10's 170 Msps sample rate and 80 dB SFDR make it an excellent fit for cellular basestation IF-digitizing receiver chains. According to the Analog Devices LTC2240-10 datasheet, the 1.4 GHz analog input bandwidth allows direct sampling of intermediate frequencies in the 70-300 MHz range, simplifying the analog mixer stage and reducing overall receiver bill-of-materials. The 60.6 dB SNR floor is sufficient for UMTS, LTE, and 5G NR early-stage channel digitizers where cost dominates the SNR budget. The 64-QFN footprint is pin-compatible with the higher-resolution LTC2184IUP (12-bit) and LTC2156IUP-14 (14-bit), so a single PCB layout can support a tiered product line.
おすすめ
Cable Head-End QAM Demodulator
Cable television head-end digitizers demand wide SFDR to resolve dense QAM constellations. The LTC2240IUP-10's 80 dB SFDR across the IF band makes it a strong choice for DOCSIS 3.1 upstream and downstream channel digitizers. According to the LTC2240 datasheet, the differential analog inputs accept the high common-mode levels typical of cable modem termination systems (CMTS) while the LVDS output mode minimizes digital switching noise into adjacent channels. The single 3V supply simplifies the rack-mounted head-end power architecture. The 64-QFN footprint is shared with the LTC2156IUP-14, allowing a higher-order 14-bit version to be qualified into the same socket for premium-tier head-ends.
おすすめ
Radar IF Digitizer
Pulsed-radar IF digitizers require wide SFDR and fast overdrive recovery to handle short transient events. The LTC2240IUP-10's pipelined core and 1.4 GHz input bandwidth allow direct sampling of radar IF strips at 100-250 MHz, eliminating analog demodulator stages. According to the LTC2240-10 datasheet, the LVDS output mode provides deterministic latency for moving-target-indicator (MTI) processing, while the single 3V supply eases integration with field-deployable radar systems. Pin-compatible LTC2184IUP and LTC2156IUP-14 alternatives can be fitted to the same PCB to deliver higher dynamic range for surveillance radar versus the lower-cost 10-bit part for proximity fuses.
おすすめ
Software-Defined Radio IF Sampling
Software-defined radio (SDR) platforms leverage direct digitizers to replace multiple analog demodulation stages. The LTC2240IUP-10's 170 Msps sample rate and 60.6 dB SNR are sufficient to digitize HF-to-VHF intermediate outputs of front-end tuners, enabling a single ADC to feed downstream DSP for multiple demodulation modes. According to the LTC2240 datasheet, the programmable gain amplifier allows input scaling for both high- and low-signal conditions, while the internal reference eliminates external reference noise coupling. The QFN-64 package is hand-solderable on breakout boards, and the same footprint accepts higher-resolution siblings.
おすすめ
Medical Imaging Front-End
Ultrasound and other medical imaging front-ends demand high spurious-free dynamic range to resolve low-contrast features. The LTC2240IUP-10's 80 dB SFDR across its input bandwidth is suitable for low-end portable ultrasound beamformers, where each channel requires its own ADC at moderate sample rates. According to the Analog Devices datasheet, the single 3V supply and small QFN-64 package allow dense array placement on multi-channel imaging boards, while the LVDS output mode minimizes crosstalk into adjacent channels. Pin-compatible LTC2184IUP and LTC2156IUP-14 alternatives can be qualified for higher-tier imaging systems requiring greater bit depth.
おすすめ
High-Speed Data Acquisition Card
PCIe and PXIe data acquisition cards for laboratory instruments often demand a 100-200 Msps ADC per channel. The LTC2240IUP-10's 170 Msps rate, 60.6 dB SNR, and LVDS/CMOS-selectable output are well matched to FPGA-based acquisition cards, where the LVDS mode eases timing closure on the digital interface. According to the LTC2240-10 datasheet, the internal sample-and-hold, programmable gain, and internal reference reduce external component count by approximately 8-10 parts versus a discrete equivalent. The 64-QFN footprint is the same outline as the higher-resolution LTC2146IUP-14 and LTC2184IUP, enabling a tiered product family built on one PCB.
おすすめ
Spectrum Analyzer IF Digitizer
Modern swept and FFT spectrum analyzers digitize IF signals directly at 100-200 Msps to replace analog detector stages. The LTC2240IUP-10's 1.4 GHz analog input bandwidth and 80 dB SFDR enable wide-span spectrum analysis without preselector filtering. According to the LTC2240-10 datasheet, the differential analog inputs reject common-mode noise from switch-mode power supplies in portable analyzer enclosures, while the single 3V supply keeps the input section simple. The 64-QFN package allows the ADC to be placed adjacent to the FPGA on a tightly-routed 6-layer board, and pin-compatible higher-resolution LTC2184IUP and LTC2156IUP-14 variants support higher-end lab instruments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2240IUP-10 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2184IUP | LTC2156IUP-14 | LTC2221CUP | LTC2145CUP-12 | LTC2122CUK |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (UP, 9x9 mm) | 64-QFN (UP) - same | 64-QFN (UP) - same | 64-QFN (UP) - same | 64-QFN (UP) - same | 64-QFN (UK) - same QFN-64 outline, different leadframe |
| Resolution | 10 bit | 12 bit | 14 bit | 12 bit | 12 bit | 14 bit |
| Sample Rate | 170 Msps | 105 Msps | 80 Msps | 135 Msps | 80 Msps | 40 Msps |
| SNR | 60.6 dB | ~62.5 dB | ~68 dB | ~62 dB | ~62 dB | ~70 dB |
| SFDR | 80 dB | ~85 dB | ~88 dB | ~84 dB | ~84 dB | ~88 dB |
| Analog Input Bandwidth | 1.4 GHz | 1.4 GHz | 1.0 GHz | 1.0 GHz | 0.8 GHz | 0.7 GHz |
| Channels | 1 | 1 | 1 | 1 | 1 | 2 |
| Output Interface | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS |
| Supply Voltage | 3 V | 3 V | 3 V | 3 V | 3 V | 3 V |
主な差別化要因
- Highest sample rate in this QFN-64 pin-compatible ADC family （vs LTC2184IUP (12-bit/105 Msps))
- Identical QFN-64 footprint across Analog Devices ADC family （vs LTC2156IUP-14 (14-bit/80 Msps))
- Single 3V supply simplifies power architecture （vs LTC2122CUK (14-bit/40 Msps dual-channel))
設計ノート
According to the LTC2240-10 datasheet, separate analog and digital ground planes tied at a single point near the ADC are required for full 60.6 dB SNR performance. Place the analog supply decoupling (1uF + 0.1uF ceramic) within 5 mm of each VCC pin, and use a continuous unbroken ground plane under the package exposed pad, which must be soldered to a 6x6 mm copper island for thermal dissipation. Run LVDS data outputs as 100-ohm differential pairs over a continuous reference plane, and avoid routing analog inputs parallel to digital outputs.
Pair the LTC2240IUP-10 with a low-jitter clock source (sub-200 fs rms aperture jitter) to achieve rated SNR at high IF frequencies. The SNR vs input frequency relationship is SNR(dB) = 60.6 - 20*log10(F_in/Fin_at_spec) - 10*log10((2*pi*F_in*1e-9)/tjitter)^2, so at 200 MHz IF and 300 fs rms jitter the SNR degrades by approximately 1 dB. Recommended companion clocks are the Analog Devices HMC1032/HMC1034 and LTC6952/LTC6953 families, all of which meet pipelined ADC jitter budgets.
A common mistake is using a single-ended CMOS clock source. The LTC2240IUP-10 requires a differential clock input; a single-ended clock will degrade SNR by 4-6 dB and inject substrate noise into the analog front-end. Use a CMOS-to-LVDS translator such as the LTC6952 or drive the CLK+/CLK- pins directly from a low-jitter LVPECL oscillator. Also, never leave the SHDN pin floating - it must be tied to ground for normal operation or driven high for shutdown mode to keep quiescent current below datasheet limits.
According to the LTC2240-10 datasheet, the LTC2240IUP-10 consumes approximately 455 mW at 170 Msps with LVDS output, with an additional ~40 mW per enabled CMOS output pair. The exposed pad must be soldered to a 6x6 mm copper pour on a 6-layer stackup to keep junction-to-ambient thermal resistance around 28 C/W, ensuring reliable operation up to the +85C industrial maximum. Power-up sequencing is not strictly required, but powering OVCC before VCC by more than 300 mV can latch the part; use a common supply rail with parallel decoupling.
コンプライアンス情報
RoHS/REACH compliant per DigiKey listing and Analog Devices product page; lead-free #PBF finish; no AEC-Q100 qualified variant is offered
