LTC2261CUJ-12 - 12-Bit 125Msps Ultra-Low-Power ADC | Analog Devices
部品番号: LTC2261CUJ-12 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $27.5 | $27.50 |
| 10 | $24.8 | $248.00 |
| 100 | $22.1 | $2,210.00 |
| 500 | $19.95 | $9,975.00 |
| 1,000 | $18.4 | $18,400.00 |
LTC2261CUJ-12 概要
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous analog voltages into discrete digital codes at a defined sampling rate. The pipelined ADC architecture uses multiple low-resolution stages to achieve high throughput with low latency, and it occupies the middle ground between successive-approximation (SAR) converters (low speed, low power) and flash converters (very high speed, high power). In the broader taxonomy, the LTC2261CUJ-12 belongs to the high-speed pipelined ADC > data converter > signal-chain IC > mixed-signal semiconductor hierarchy.
Key features of the LTC2261CUJ-12 include selectable input ranges of 1 Vp-p to 2 Vp-p, CMOS, DDR CMOS or DDR LVDS output modes, an optional data output randomizer, an optional clock duty-cycle stabilizer, shutdown and nap power-down modes, and a serial SPI port for mode configuration. The converter is pin-compatible with the 14-bit LTC2261-14 and the 12/14-bit LTC2260 and LTC2259 family members, allowing a single PCB to address multiple resolution and speed targets.
Technically, the device combines an internal high-bandwidth track-and-hold front end with on-chip reference and a digital error-correction pipeline. The pin-compatible family lets designers trade resolution for power: LTC2261-12 runs at 125 Msps, LTC2260-12 at 105 Msps, and LTC2259-12 at 80 Msps, while a 14-bit counterpart doubles the vertical resolution at similar throughput. Output flexibility (CMOS, DDR CMOS, DDR LVDS) lets the same part mate directly with either ASICs/FPGAs using LVDS or with low-pin-count microcontrollers using CMOS.
Typical applications include cellular base-station receivers, software-defined radio, ultrasound imaging front ends, radar signal processing, and high-speed instrumentation. With 70.8 dB SNR and 85 dB SFDR, the device cleanly resolves multi-carrier IF signals and pulsed waveforms without raising the noise floor of the receive path.
When designing with this device, place the analog input coupling network as close to the AIN pins as possible, provide a solid ground plane tied to the exposed pad for thermal dissipation, and decouple AVDD/OVDD with 10 uF plus 0.1 uF ceramic capacitors within 5 mm of the supply pins. Always drive the encode clock from a low-jitter source to preserve SNR at the rated input frequency.
This page synthesizes distributor pricing, pin-compatible family alternatives, and practical design notes beyond what the manufacturer datasheet alone provides, including real-time stock and lead-time data sourced from major distributors.
ドロップイン代替品: LTC2261CUJ-12 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2261CUJ-12 （同一形状・フットプリント） — 相違点: Package, Power Dissipation, RoHS Status, Output Interface, Transition Noise.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2260CUJ-12
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2259CUJ-12
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2261CUJ-14
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$43.96 / 個
データシートを見る →LTC2260CUJ-14
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$19.4 / 個
データシートを見る →LTC2259CUJ-14
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
LTC2261IUJ-12
✅ ドロップイン✓ 在庫あり
$11.78 / 個
データシートを見る →LTC2260IUJ-12
✅ ドロップイン✓ 在庫あり
$11.75 / 個
データシートを見る →LTC2260CUJ-12#PBF
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
LTC2261CUJ-12 最大定格＆電気的特性
| 分解能 | 12 bits |
| Number of Input Channels | 1 |
| サンプリングレート | 125 Msps (125,000 kSamples/sec) |
| Architecture | Pipelined |
| SNR | 70.8 dB |
| SFDR | 85 dB |
| Full-Power Input Bandwidth | 800 MHz |
| Supply Voltage (AVDD/OVDD) | 1.8 V (1.7 V to 1.9 V) |
| Power Consumption | 124 mW |
| 入力電圧範囲 | 1 Vp-p to 2 Vp-p (selectable) |
| Output Interface | CMOS / DDR CMOS / DDR LVDS |
| Input Type | Bipolar/Differential |
| パッケージ | 40-QFN (6 mm x 6 mm) with exposed pad |
| 動作温度 | 0 C to +70 C (Commercial) |
| Configuration Interface | Serial SPI port |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant (PBF suffix) |
LTC2261CUJ-12 ピン構成
| ピン 1 | AIN+ — Differential analog input positive |
| ピン 2 | AIN- — Differential analog input negative |
| ピン 3 | GND — Analog ground |
| ピン 4 | AVDD — Analog 1.8 V supply |
| ピン 5 | VCM — Common-mode voltage output (0.9 V typ.) |
| ピン 6 | REFT — Top reference decoupling |
| ピン 7 | REFB — Bottom reference decoupling |
| ピン 8 | GND — Analog ground |
| ピン 9 | AVDD — Analog 1.8 V supply |
| ピン 10 | ENC+ — Encode clock input positive |
| ピン 11 | ENC- — Encode clock input negative |
| ピン 12 | GND — Clock ground |
| ピン 13 | OVDD — Output 1.8 V supply |
| ピン 14 | GND — Digital ground |
| ピン 15 | D0 — Data output bit 0 (LSB) |
| ピン 16 | D1 — Data output bit 1 |
| ピン 17 | D2 — Data output bit 2 |
| ピン 18 | D3 — Data output bit 3 |
| ピン 19 | D4 — Data output bit 4 |
| ピン 20 | D5 — Data output bit 5 |
| ピン 21 | D6 — Data output bit 6 |
| ピン 22 | D7 — Data output bit 7 |
| ピン 23 | D8 — Data output bit 8 |
| ピン 24 | D9 — Data output bit 9 |
| ピン 25 | D10 — Data output bit 10 |
| ピン 26 | D11 — Data output bit 11 (MSB) |
| ピン 27 | DRCLK — Data ready clock output |
| ピン 28 | OVDD — Output 1.8 V supply |
| ピン 29 | OGND — Output ground |
| ピン 30 | CS — SPI chip select (active low) |
| ピン 31 | SCK — SPI serial clock |
| ピン 32 | SDI — SPI serial data input |
| ピン 33 | SDO — SPI serial data output |
| ピン 34 | SHDN — Shutdown mode control (active high) |
| ピン 35 | NAP — Nap mode control (active high) |
| ピン 36 | MODE — Output mode select (CMOS/DDR CMOS/LVDS) |
| ピン 37 | RAND — Data output randomizer enable |
| ピン 38 | DCS — Duty-cycle stabilizer enable |
| ピン 39 | OVDD — Output 1.8 V supply |
| ピン 40 | GND — Ground / exposed pad |
主な用途
LTC2261CUJ-12 の用途: 6 件s: Cellular Base-Station Receiver, Software Defined Radio (SDR), Ultrasound Imaging Front End, Radar Signal Processing, High-Speed Instrumentation, Industrial Non-Destructive Testing.
Cellular Base-Station Receiver
The LTC2261CUJ-12 is well suited for cellular base-station IF digitizer chains where 70.8 dB SNR and 85 dB SFDR preserve the multi-carrier dynamic range required by 4G LTE and 5G NR receivers. With 125 Msps sampling and an 800 MHz full-power input bandwidth, the converter can capture wide-bandwidth intermediate-frequency signals after the analog mixer stage, while the 124 mW power consumption keeps the per-channel thermal budget manageable in multi-channel MIMO designs. The pin-compatible 14-bit LTC2261CUJ-14 allows upgrade paths for carriers demanding higher resolution without PCB changes. Designer drives faster -20 percent oversampling margin. Place the AIN coupling network within 5 mm of the analog input pins and tie the exposed pad to a solid ground plane to maintain SNR at the rated input frequency.
おすすめ
Software Defined Radio (SDR)
The LTC2261CUJ-12's 12-bit resolution and 125 Msps sampling rate make it ideal for software-defined radio platforms that digitize a wide swath of spectrum for downstream digital tuning. The 70.8 dB SNR floor enables reception of weak signals adjacent to high-power interferers, which is critical in crowded HF/VHF/UHF bands. The selectable 1 Vp-p to 2 Vp-p input range accommodates front-end LNA outputs without requiring an additional variable-gain stage, while the SPI port lets the host FPGA dynamically reconfigure modes during channel scans. The clock duty-cycle stabilizer maintains conversion accuracy even when the FPGA-derived encode clock has imperfect 50-50 symmetry, preserving SNR across the input bandwidth.
おすすめ
Ultrasound Imaging Front End
In ultrasound imaging systems the LTC2261CUJ-12 digitizes the received echo signals at rates up to 125 Msps, capturing the wide-bandwidth pulse-echo responses needed for high axial-resolution imaging. The 85 dB SFDR preserves contrast between small and large reflectors, while the 800 MHz input bandwidth accommodates the broadband LNA outputs typical of piezoelectric transducer preamps. The low 124 mW power dissipation keeps per-channel thermal loading acceptable in dense multi-channel probe heads, and the pin-compatible LTC2260CUJ-12 (103 mW at 105 Msps) supports lower-power portable probes without sacrificing the same QFN-40 PCB layout. The CMOS / DDR CMOS / DDR LVDS output flexibility lets the same ADC mate with either an FPGA-based beamformer or an ASIC front-end.
おすすめ
Radar Signal Processing
The LTC2261CUJ-12 fits pulsed-Doppler and FMCW radar front ends that demand wide instantaneous bandwidth and high spurious-free dynamic range to resolve small targets in clutter. Its 85 dB SFDR prevents strong clutter returns from generating intermodulation spurs that mask nearby weak targets, while the 70.8 dB SNR establishes the noise-limited detection range of the radar link. The 1.8 V single-supply operation simplifies power-tree design in vehicular and avionics radar modules, and the pin-compatible LTC2259CUJ-12 (80 Msps, 87 mW) supports lower-bandwidth radar altimeter applications in the same footprint. The exposed pad package provides the thermal dissipation needed for continuous-wave radar modes where the ADC runs at 100% utilization.
おすすめ
High-Speed Instrumentation
The LTC2261CUJ-12 serves high-speed digital oscilloscopes, spectrum analyzers, and data-acquisition cards that need to capture repetitive or single-shot wideband signals with high fidelity. The 800 MHz full-power input bandwidth exceeds the Nyquist limit of the 125 Msps sample rate, allowing undersampling of IF signals in heterodyne instrument architectures. The 12-bit resolution provides approximately 72 dB theoretical SNR (6.02N+1.76 dB), and the measured 70.8 dB approaches this ideal, leaving minimal quantization-noise contribution in the captured waveform. The SPI configuration port enables instrument calibration routines to switch input ranges on the fly without manual recalibration, and shutdown/nap modes reduce power during idle display intervals.
おすすめ
Industrial Non-Destructive Testing
The LTC2261CUJ-12 digitizes ultrasonic and eddy-current probe signals in industrial non-destructive testing (NDT) equipment, where 70.8 dB SNR and 85 dB SFDR preserve the small flaw echoes against the large background signal from the bulk material. The wide 800 MHz analog input bandwidth supports high-frequency ultrasonic probes used for fine crack detection in aerospace components, while the 125 Msps sampling rate captures full pulse-echo waveforms with minimal aliasing artifacts. The commercial 0 C to +70 C operating range suits benchtop and rack-mounted NDT stations, and the pin-compatible LTC2261IUJ-12 (industrial -40 C to +85 C) extends coverage to field-portable inspection equipment operating in extreme ambient conditions.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2261CUJ-12 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2260CUJ-12 | LTC2259CUJ-12 | LTC2261CUJ-14 | LTC2261IUJ-12 |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 40-QFN (6x6 mm) | 40-QFN (6x6 mm) - same | 40-QFN (6x6 mm) - same | 40-QFN (6x6 mm) - same | 40-QFN (6x6 mm) - same |
| Resolution | 12 bits | 12 bits | 12 bits | 14 bits | 12 bits |
| Sampling Rate | 125 Msps | 105 Msps | 80 Msps | 125 Msps | 125 Msps |
| SNR | 70.8 dB | 70.8 dB | 70.8 dB | 73.4 dB | 70.8 dB |
| SFDR | 85 dB | 85 dB | 85 dB | 85 dB | 85 dB |
| Power Consumption | 124 mW | 103 mW | 87 mW | 124 mW | 124 mW |
| Operating Temperature | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C | -40 C to +85 C |
主な差別化要因
- Highest sampling rate in pin-compatible QFN-40 family （vs LTC2260CUJ-12)
- Lower power than competing 125 Msps 12-bit ADCs （vs Generic 125 Msps 12-bit ADC competitors)
- Pin-compatible upgrade path to 14-bit resolution （vs LTC2261CUJ-14)
- Industrial temperature variant available in same package （vs LTC2261IUJ-12)
設計ノート
Place the analog input coupling network within 5 mm of the AIN+ and AIN- pins, using a symmetric layout to preserve the 70.8 dB SNR. Decouple each AVDD pin with a 10 uF ceramic plus a 0.1 uF X7R ceramic within 2 mm of the package, and provide a solid ground plane tied to the exposed thermal pad with at least 8 thermal vias for heat removal. Keep the encode clock trace length-matched to the ENC+/ENC- pins and isolated from noisy digital outputs.
Drive the encode clock from a low-jitter source (jitter < 500 fs RMS) to preserve SNR at the rated input frequency. Enable the on-chip clock duty-cycle stabilizer (DCS pin) when the clock source cannot guarantee 50% duty cycle, otherwise SNR degrades by 1-2 dB. For LVDS output mode, terminate the differential outputs with 100 A near the receiver to prevent reflections.
Do not apply analog input signals before the AVDD/OVDD supplies have ramped - the input ESD structures can be damaged. Always respect the input common-mode voltage (VCM = 0.9 V typ.) and AC-couple through a transformer or driver amp that establishes this common mode. The shutdown (SHDN) and nap (NAP) pins must not be left floating - tie them to ground through a 10 kOhm resistor if unused to prevent accidental power-down from noise injection.
Estimated: at 124 mW power dissipation on a 40-QFN package (theta_JA approximately 40 mm per JEDEC 51 with the exposed pad soldered), the junction temperature rises only 5 C above ambient, so no heatsink is required. However, in enclosed housings with poor airflow, derate by ensuring ambient stays below 65 C to maintain the 0 C to +70 C commercial temperature grade with adequate margin.
コンプライアンス情報
RoHS compliant per #PBF suffix and Analog Devices product page. Lead-free finish (eCUFN). Not AEC-Q100 qualified - the IUJ industrial-temp variant is recommended for automotive applications but is not AEC-Q100 qualified either. Halogen-free status not explicitly stated in provided data.
