LTC2263CUJ-12 - 12-Bit 25Msps Dual ADC | Analog Devices
部品番号: LTC2263CUJ-12 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.65 | $256.50 |
| 100 | $22.78 | $2,278.00 |
| 500 | $21.1 | $10,550.00 |
| 1,000 | $19.2 | $19,200.00 |
LTC2263CUJ-12 概要
What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed Nyquist ADC architecture that resolves the input sample in a sequence of low-resolution stage conversions. Each stage produces a partial digital result and a residue that is amplified and passed to the next stage. This pipelining allows one conversion to be in progress while the next sample is being acquired, giving sample rates from a few Msps up to several hundred Msps. Pipelined ADCs sit in the signal-chain hierarchy: sensor -> analog front end -> ADC -> digital processing. They are the workhorse architecture for communications, imaging, and instrumentation.
Key features of the LTC2263CUJ-12 include 800 MHz full-power input bandwidth, flexible serial LVDS digital outputs (1-lane or 2-lane mode), an SPI port for per-channel configuration of gain, offset, and channel selection, and pin compatibility with the 14-bit LTC2263-14 and the higher-speed LTC2264-12 (40 Msps) / LTC2265-12 (65 Msps) family members. CMOS and DDR LVDS output modes are selectable.
Typical applications include cellular basestation receivers, software-defined radio (SDR), portable medical imaging, low-power ultrasound, multi-channel data acquisition, and handheld test instrumentation where dual-channel simultaneous sampling reduces system cost and board area. The wide input bandwidth also allows undersampling of IF signals in communications systems.
When designing with the LTC2263CUJ-12, decouple AVDD and DVDD supplies with 1 muF ceramic capacitors placed as close to the pins as possible, and provide a clean clock source with low jitter - the SNR floor of an ADC is dominated by the aperture uncertainty of the sampling clock. Use the exposed pad as the primary thermal and ground return path.
This page combines verified distributor stock data, drop-in pin-compatible alternatives, and practical design notes that go beyond what the manufacturer datasheet alone provides - useful for engineers evaluating the LTC2263-12 family for new designs or second-source qualification.
ドロップイン代替品: LTC2263CUJ-12 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2263CUJ-12 （同一形状・フットプリント） — 相違点: Package, Input Type, Operating Temperature, Number of Channels, Operating Temperature Range.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2263CUJ-14
✅ ドロップイン✓ 在庫あり
$18.24 / 個
データシートを見る →LTC2264CUJ-12
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2265CUJ-12
✅ ドロップイン✓ 在庫あり
$22.4 / 個
データシートを見る →LTC2262IUJ-12
✅ ドロップイン✓ 在庫あり
$20.55 / 個
データシートを見る →LTC2260IUJ-12
✅ ドロップイン✓ 在庫あり
$11.75 / 個
データシートを見る →LTC2263CUJ-12 最大定格＆電気的特性
| 分解能 | 12 bits |
| Number of Channels | 2 (simultaneous sampling) |
| Architecture | Pipelined |
| Sample Rate (per channel) | 25 Msps |
| Input Bandwidth | 800 MHz full power |
| INL (typical) | ±0.3 LSB |
| DNL (typical) | ±0.1 LSB |
| Transition Noise | 0.3 LSB RMS |
| Missing Codes | None over temperature |
| Output Interface | Serial LVDS (1-lane / 2-lane), CMOS option |
| 電源電圧 | 1.8 V (AVDD, DVDD) |
| Power Dissipation | approximately 30 mW per channel at 25 Msps |
| 動作温度 | 0°C to +70°C (commercial 'C' grade) |
| パッケージ | 40-pin QFN (6 mm x 6 mm) with exposed pad |
| Configuration Interface | SPI |
| Power-Saving Modes | Shutdown and Nap |
| RoHS ステータス | Compliant (PBF suffix) |
LTC2263CUJ-12 ピン構成
| ピン 1 | GND — Ground (exposed pad also serves as primary ground) |
| ピン 2 | IN1+ — Channel 1 differential analog input positive |
| ピン 3 | IN1- — Channel 1 differential analog input negative |
| ピン 4 | AVDD — Analog 1.8 V supply |
| ピン 5 | GND — Ground |
| ピン 6 | CM1 — Channel 1 common-mode voltage bypass |
| ピン 7 | GND — Ground |
| ピン 8 | IN2+ — Channel 2 differential analog input positive |
| ピン 9 | IN2- — Channel 2 differential analog input negative |
| ピン 10 | AVDD — Analog 1.8 V supply |
| ピン 11 | GND — Ground |
| ピン 12 | CM2 — Channel 2 common-mode voltage bypass |
| ピン 13 | GND — Ground |
| ピン 14 | SENSE — Reference voltage sense pin |
| ピン 15 | REFT1 — Reference decoupling top |
| ピン 16 | REFB1 — Reference decoupling bottom |
| ピン 17 | REFT2 — Reference decoupling top |
| ピン 18 | REFB2 — Reference decoupling bottom |
| ピン 19 | AVDD — Analog 1.8 V supply |
| ピン 20 | GND — Ground |
| ピン 21 | OGND — Output driver ground |
| ピン 22 | OVDD — Output driver supply |
| ピン 23 | NC — Not connected (per datasheet) |
| ピン 24 | OUT2- — Channel 2 LVDS serial output negative |
| ピン 25 | OUT2+ — Channel 2 LVDS serial output positive |
| ピン 26 | OUT1- — Channel 1 LVDS serial output negative |
| ピン 27 | OUT1+ — Channel 1 LVDS serial output positive |
| ピン 28 | OGND — Output driver ground |
| ピン 29 | OVDD — Output driver supply |
| ピン 30 | CLKOUT- — Clock output LVDS negative (for cascaded ADCs) |
| ピン 31 | CLKOUT+ — Clock output LVDS positive |
| ピン 32 | OGND — Output driver ground |
| ピン 33 | OVDD — Output driver supply |
| ピン 34 | GND — Ground |
| ピン 35 | CLK- — Differential clock input negative |
| ピン 36 | CLK+ — Differential clock input positive |
| ピン 37 | GND — Ground |
| ピン 38 | CS — SPI chip select (active low) |
| ピン 39 | SCK — SPI serial clock |
| ピン 40 | SDO — SPI serial data output |
主な用途
LTC2263CUJ-12 の用途: 6 件s: Cellular Basestation Receivers, Software Defined Radio (SDR), Portable Medical Imaging, Low-Power Multi-Channel Data Acquisition, Handheld Test and Measurement Instrumentation, Communications IF Sampling.
Cellular Basestation Receivers
The LTC2263CUJ-12 fits cellular basestation receiver channels because its 25 Msps per channel rate covers 3G UMTS (3.84 Mcps) and early 4G LTE (5 Mcps) signal bandwidths with margin, while 800 MHz full-power input bandwidth supports undersampling of 70 MHz or 140 MHz IF stages. Dual simultaneously-sampling channels digitize I and Q paths directly, halving board area versus two discrete ADCs. Low 30 mW per channel dissipation eases thermal budgets in dense 4-channel or 8-channel MIMO receiver cards running at elevated ambient. The SPI port allows per-channel gain calibration during production, trimming out front-end gain mismatch.
おすすめ
Software Defined Radio (SDR)
In software defined radio platforms the LTC2263CUJ-12 provides dual 25 Msps sampling of I/Q baseband or low-IF signals. The 800 MHz analog input bandwidth enables direct IF sampling at common IF frequencies (10.7 MHz, 21.4 MHz, 70 MHz), simplifying receiver architecture by eliminating a downconversion stage. The LVDS output interface streams data into FPGAs such as Xilinx Spartan-6 or Cyclone IV with minimal pin count. Low 0.3 LSB RMS transition noise preserves demodulation SNR for narrowband digital modes like PSK31 or DVB-T receivers. Pin compatibility with the 14-bit LTC2263-14 lets designers scale dynamic range later without board rework.
おすすめ
Portable Medical Imaging
The LTC2263CUJ-12 supports portable medical imaging systems including handheld ultrasound and point-of-care diagnostic devices. Dual-channel simultaneous sampling digitizes two receive beams per chip, reducing per-channel power to roughly 30 mW which is critical for battery-operated scanners. Shutdown and nap modes drop power below 1 mW between scan acquisitions. The 12-bit resolution is sufficient for mid-tier B-mode imaging where dynamic range requirements are moderate; the pin-compatible 14-bit LTC2263CUJ-14 is available for harmonic imaging where finer quantization matters. Industrial-temperature grade is unnecessary for cart-based devices in climate-controlled clinical environments.
おすすめ
Low-Power Multi-Channel Data Acquisition
For multi-channel data acquisition modules the LTC2263CUJ-12 doubles channel density per PCB footprint, with two simultaneous-sampling 25 Msps channels in one 6 mm x 6 mm QFN-40 package. Each channel draws approximately 30 mW at full speed, allowing 8-channel systems to stay under 250 mW of ADC power dissipation - practical for compact USB-powered DAQ modules. The SPI port enables daisy-chained configuration across multiple ADCs sharing one CS line, simplifying FPGA or microcontroller interfacing. Pin compatibility with the LTC2265CUJ-12 (65 Msps) preserves layout when channel density must be reduced while sample rate increases.
おすすめ
Handheld Test and Measurement Instrumentation
Handheld oscilloscopes, spectrum analyzers, and arbitrary waveform generators use the LTC2263CUJ-12 for two-channel acquisition at 25 Msps. The compact QFN-40 footprint fits into pocket-sized form factors while drawing only 60 mW total. The LVDS output reduces EMI relative to parallel CMOS, an important consideration in battery-powered instruments where radiated noise couples into sensitive analog front ends. Industrial-temperature drop-in LTC2260IUJ-12 or LTC2262IUJ-12 are available when the instrument must operate in field environments with extreme ambient temperatures.
おすすめ
Communications IF Sampling
The 800 MHz analog input bandwidth of the LTC2263CUJ-12 enables undersampling of IF signals at 21.4 MHz, 70 MHz, or 140 MHz, eliminating a second mixer stage in radio receivers. Dual channels digitize two antenna polarizations simultaneously in diversity receivers. The 0.3 LSB RMS transition noise floor combined with 12-bit resolution delivers approximately 70 dB SNR, adequate for many narrowband communications standards. Pin compatibility with the 65 Msps LTC2265CUJ-12 lets designers reuse PCB layout when migrating to wider-bandwidth signals.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2263CUJ-12 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2263CUJ-14 | LTC2264CUJ-12 | LTC2265CUJ-12 | LTC2262IUJ-12 | LTC2260IUJ-12 |
|---|---|---|---|---|---|---|
| Package | 40-QFN (6x6) | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 12 bits | 14 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Sample Rate (per channel) | 25 Msps | 25 Msps | 40 Msps | 65 Msps | 150 Msps | 105 Msps |
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Operating Temperature | 0°C to +70°C (commercial) | 0°C to +70°C (commercial) | 0°C to +70°C (commercial) | 0°C to +70°C (commercial) | -40°C to +85°C (industrial) | -40°C to +85°C (industrial) |
| Input Bandwidth | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 900 MHz | 800 MHz |
| Output Interface | Serial LVDS / CMOS | Serial LVDS / CMOS | Serial LVDS / CMOS | Serial LVDS / CMOS | Serial LVDS / CMOS | Serial LVDS / CMOS |
| Power per Channel (typ) | approximately 30 mW | approximately 30 mW | approximately 45 mW | approximately 65 mW | approximately 130 mW | approximately 95 mW |
主な差別化要因
- Pin compatibility across the LTC2263/4/5-12 family allows resolution and speed scaling （vs LTC2265CUJ-12 (65 Msps))
- Dual simultaneously-sampling channels halve PCB area versus two discrete ADCs （vs Two single-channel ADCs in 20-QFN)
- Industrial-temperature drop-in variants exist for harsh environments （vs LTC2262IUJ-12 (industrial, 150 Msps))
設計ノート
Decouple AVDD and DVDD with 1 muF ceramic capacitors placed within 2 mm of each supply pin, plus a 0.1 muF high-frequency bypass cap in parallel. The exposed pad (EP) must be soldered to a continuous ground plane to provide both thermal dissipation and the low-inductance ground return for the reference and clock circuits. Separate analog and digital ground planes meeting only at the EP prevent digital switching noise from coupling into the analog input path.
ADC SNR is dominated by clock jitter, not by ADC intrinsic noise. Estimated: for the LTC2263CUJ-12 to achieve its rated SNR at 70 MHz IF input, the sampling clock must have less than 0.5 ps RMS jitter. Use a dedicated low-jitter clock generator like the AD9523 or ADF4350 rather than an FPGA-generated clock. Drive the CLK+/CLK- pins with a differential signal; a single-ended CMOS clock typically yields 5-10 dB worse SNR than a properly terminated differential clock.
Route analog differential input pairs (IN1+/IN1-, IN2+/IN2-) as length-matched 100 ohm differential transmission lines with ground reference on each side. Keep digital LVDS output traces away from analog input traces to avoid capacitive coupling of the 1 GHz edge rates into the sensitive input front end. The 40-QFN exposed pad requires at least 8 thermal vias (0.3 mm diameter) on the PCB for adequate heat sinking when operating at full sample rate and full temperature.
Terminate the LVDS outputs with 100 ohm differential impedance near the receiver (FPGA pins) rather than near the ADC to maximize signal integrity at the receiver. For multi-ADC synchronization, use the LTC2263CUJ-12's CLKOUT+/CLKOUT- pins to daisy-chain clocks between chips, ensuring deterministic sample-to-sample alignment across channels. Use the SPI port's SDO/SCK/CS lines to apply per-channel gain and offset calibration codes after PCB assembly to compensate for front-end gain mismatch.
コンプライアンス情報
RoHS compliance per the #PBF suffix in the manufacturer part number. Industrial-temperature grade variants (LTC2263IUJ-12 and the LTC2260/LTC2262 family) are available for harsher environments. Halogen-free status not explicitly stated in available data.
