LTC2263CUJ-14 - Dual 14-Bit 25Msps Low-Power ADC | Analog Devices
部品番号: LTC2263CUJ-14 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.65 | $256.50 |
| 100 | $22.8 | $2,280.00 |
| 500 | $20.52 | $10,260.00 |
| 1,000 | $18.24 | $18,240.00 |
LTC2263CUJ-14 概要
A dual ADC (dual-channel analog-to-digital converter) is a component that integrates two independent sampling channels on a single die, allowing simultaneous capture of two analog signals at the same clock instant. This dual architecture is widely used in communications receivers where I/Q baseband signals must be sampled synchronously, in diversity antenna systems, and in any multi-channel instrumentation application. The LTC2263CUJ-14 belongs to the broader pipelined ADC family within the data acquisition IC category, which sits hierarchically under converter ICs and signal chain semiconductors.
The device includes selectable 1V P-P to 2V P-P input ranges, an 800 MHz full-power bandwidth sample-and-hold, and serial LVDS outputs configurable for 1-bit or 2-bit per channel modes. DC accuracy is excellent, with ±1 LSB INL (typical), ±0.3 LSB DNL (typical), and no missing codes over temperature. The low 1.2 LSB RMS transition noise ensures clean digital output even at full-scale inputs.
Pin-compatible 14-bit and 12-bit versions allow system designers to migrate between resolutions without PCB rework, while the integrated SPI configuration port, shutdown, and nap modes simplify power management. According to the manufacturer datasheet, the recommended PCB layout requires a clean unbroken ground plane with the first internal layer dedicated to ground beneath the ADC.
Typical applications include software-defined radio (SDR), cellular base-station receivers, portable instrumentation, and low-power medical imaging. The wide 800 MHz input bandwidth makes the part particularly attractive for undersampling IF signals in communications receivers.
When laying out the PCB, ensure that analog input traces are routed as differential pairs over a continuous ground plane to preserve the 73.7 dB SNR. Place the 1.8V supply decoupling network within 5 mm of the AVDD pins to suppress switching-noise coupling.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives from the same ADC family, and practical PCB/layout guidance that goes beyond what is found in the manufacturer datasheet alone.
ドロップイン代替品: LTC2263CUJ-14 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2263CUJ-14 （同一形状・フットプリント） — 相違点: Package, Resolution, Configuration Interface, Power Dissipation, Sample Rate.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2263CUJ-14#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2263CUJ-14#TRPBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2263CUJ-12
✅ ドロップイン✓ 在庫あり
$19.2 / 個
データシートを見る →LTC2264CUJ-14
✅ ドロップイン✓ 在庫あり
$27.5 / 個
データシートを見る →LTC2260CUJ-14
✅ ドロップイン✓ 在庫あり
$19.4 / 個
データシートを見る →LTC2263CUJ-14 最大定格＆電気的特性
| 分解能 | 14 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sample Rate | 25 Msps |
| Architecture | Pipelined |
| 電源電圧 | 1.8 V (single) |
| Total Power Consumption | 94 mW (47 mW per channel) |
| SNR | 73.7 dB |
| SFDR | 90 dB |
| INL (typical) | ±1 LSB |
| DNL (typical) | ±0.3 LSB |
| Transition Noise | 1.2 LSB RMS |
| Input Range | 1 V P-P to 2 V P-P (selectable) |
| Full Power Input Bandwidth | 800 MHz |
| Digital Output | Serial LVDS (1 or 2 bits per channel) |
| Configuration Interface | Serial SPI port |
| パッケージ | 40-pin QFN (6 mm x 6 mm) |
| 動作温度 | 0C to +70C (commercial grade) |
| Pin Compatibility | Yes - with 12-bit versions in same family |
LTC2263CUJ-14 ピン構成
| ピン 1 | GND — Ground (digital) |
| ピン 2 | SENSE — Reference mode select |
| ピン 3 | VDD — 1.8V analog supply |
| ピン 4 | OGND — Output driver ground |
| ピン 5 | OVDD — Output driver supply |
| ピン 6 | CLKOUT- — LVDS clock output (negative) |
| ピン 7 | CLKOUT+ — LVDS clock output (positive) |
| ピン 8 | OF- — LVDS frame output (negative) |
| ピン 9 | OF+ — LVDS frame output (positive) |
| ピン 10 | DB0- — LVDS data output bit 0 (negative) |
| ピン 11 | DB0+ — LVDS data output bit 0 (positive) |
| ピン 12 | DB1- — LVDS data output bit 1 (negative) |
| ピン 13 | DB1+ — LVDS data output bit 1 (positive) |
| ピン 14 | DB2- — LVDS data output bit 2 (negative) |
| ピン 15 | DB2+ — LVDS data output bit 2 (positive) |
| ピン 16 | DB3- — LVDS data output bit 3 (negative) |
| ピン 17 | DB3+ — LVDS data output bit 3 (positive) |
| ピン 18 | GND — Ground (digital) |
| ピン 19 | DB4- — LVDS data output bit 4 (negative) |
| ピン 20 | DB4+ — LVDS data output bit 4 (positive) |
| ピン 21 | DB5- — LVDS data output bit 5 (negative) |
| ピン 22 | DB5+ — LVDS data output bit 5 (positive) |
| ピン 23 | DB6- — LVDS data output bit 6 (negative) |
| ピン 24 | DB6+ — LVDS data output bit 6 (positive) |
| ピン 25 | SDI — SPI serial data input |
| ピン 26 | SCK — SPI serial clock input |
| ピン 27 | CS — SPI chip select (active low) |
| ピン 28 | SDO — SPI serial data output |
| ピン 29 | GND — Ground (analog) |
| ピン 30 | VA+ — Channel A positive analog input |
| ピン 31 | VA- — Channel A negative analog input |
| ピン 32 | GND — Ground (analog) |
| ピン 33 | VB+ — Channel B positive analog input |
| ピン 34 | VB- — Channel B negative analog input |
| ピン 35 | GND — Ground (analog) |
| ピン 36 | REFT — Reference decoupling top |
| ピン 37 | REFB — Reference decoupling bottom |
| ピン 38 | MODE — Output mode select (1-lane / 2-lane) |
| ピン 39 | CLK- — LVDS clock input (negative) |
| ピン 40 | CLK+ — LVDS clock input (positive) |
主な用途
LTC2263CUJ-14 の用途: 6 件s: Software-Defined Radio (SDR) Receiver, Cellular Base-Station Receiver, Portable Instrumentation and Data Acquisition, Medical Ultrasound Imaging Front-End, Industrial Vibration and Acoustic Monitoring, Multi-Channel Spectrum Analyzer / Signal Intelligence.
Software-Defined Radio (SDR) Receiver
The LTC2263CUJ-14 fits SDR receiver designs because its 800 MHz full-power input bandwidth enables direct undersampling of IF signals in HF/VHF bands, eliminating downconversion mixer stages. The dual simultaneous-sampling channels capture I and Q baseband signals at the same clock instant, preserving phase coherence required for demodulation. With 73.7 dB SNR and 90 dB SFDR, the part cleanly resolves weak signals in the presence of strong adjacent interferers - critical for crowded amateur radio and spectrum-monitoring bands. The serial LVDS outputs minimize FPGA pin count, and the 94 mW total power consumption is acceptable for portable SDR dongles and field-deployable receivers.
おすすめ
Cellular Base-Station Receiver
In cellular base-station receiver designs the LTC2263CUJ-14 digitizes the I and Q analog outputs of the dual downconversion chain with 73.7 dB SNR that exceeds the dynamic-range requirements of 3G/4G receiver sensitivity specifications. The 25 Msps per-channel rate accommodates multiple adjacent UMTS/LTE carrier bandwidths after digital filtering, while the 90 dB SFDR prevents false-channel decoding from strong blocker signals. Single 1.8 V supply simplifies power tree design, and the 40-QFN 6x6mm footprint allows compact placement near the RF section. The SPI configuration port enables firmware-driven input-range and lane-mode selection during factory calibration.
おすすめ
Portable Instrumentation and Data Acquisition
The LTC2263CUJ-14 is well-suited to portable data-acquisition systems where two sensor channels must be captured synchronously, such as two-axis vibration analysis, dual-channel ultrasound front-ends, or portable oscilloscope channels. Its 94 mW total power consumption extends battery life in handheld instruments, while 73.7 dB SNR provides more than 11.5 effective bits of dynamic range. The shutdown and nap modes - controllable via the SPI port - allow further power reduction when the ADC is not actively sampling, which is essential for duty-cycled measurement loops. The 40-QFN package is compatible with handheld-instrument board densities.
おすすめ
Medical Ultrasound Imaging Front-End
Portable and handheld ultrasound probes benefit from the LTC2263CUJ-14's dual simultaneous-sampling architecture, which captures echo pairs from phased-array transducer elements with deterministic phase alignment. The 73.7 dB SNR contributes directly to penetration depth and contrast sensitivity, while the 1.2 LSB RMS transition noise ensures that subtle tissue echoes are not buried in quantisation noise. The 25 Msps rate supports mid-band imaging up to 12 MHz IF when paired with appropriate anti-alias filtering. Low power (94 mW) keeps thermal dissipation acceptable in patient-contact probes.
おすすめ
Industrial Vibration and Acoustic Monitoring
The LTC2263CUJ-14 supports dual-axis MEMS accelerometer and microphone array digitisation in predictive-maintenance systems, where simultaneous capture of two orthogonal vibration axes is essential for fault diagnosis. With 800 MHz input bandwidth and 73.7 dB SNR, the part cleanly digitises vibration signals from low-frequency bearing defects through mid-frequency gear-mesh harmonics. The wide 1-2 V P-P programmable input range adapts to different MEMS output levels without external attenuators. Nap and shutdown modes reduce power during idle periods between rest sensor polls, extending field-deployment battery life.
おすすめ
Multi-Channel Spectrum Analyzer / Signal Intelligence
Spectrum analyzers and signal-intelligence receivers can use multiple LTC2263CUJ-14 devices in parallel to build wideband capture systems, since each dual ADC provides two phase-coherent channels with 73.7 dB SNR and 90 dB SFDR. The serial LVDS outputs route cleanly to FPGAs over long board traces with minimal EMI susceptibility. The 800 MHz full-power bandwidth allows each pair of channels to digitise a substantial instantaneous bandwidth after FFT processing, while the 1.8 V single supply simplifies thermal and EMI design in dense multi-board racks. Pin compatibility with the LTC2264CUJ-14 and LTC2265CUJ-14 offers future-proof upgrade paths.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2263CUJ-14 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2263CUJ-14#PBF | LTC2263CUJ-14#TRPBF | LTC2263CUJ-12 | LTC2264CUJ-14 | LTC2260CUJ-14 |
|---|---|---|---|---|---|---|
| Package | 40-QFN (6x6) | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 14 bit | 14 bit | 14 bit | 12 bit | 14 bit | 14 bit |
| Sample Rate | 25 Msps | 25 Msps | 25 Msps | 25 Msps | 40 Msps | 105 Msps |
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 |
| SNR | 73.7 dB | 73.7 dB | 73.7 dB | ~71 dB | 73.7 dB | 73.7 dB |
| Total Power Consumption | 94 mW | 94 mW | 94 mW | 94 mW | 113 mW | 140 mW (approx) |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
主な差別化要因
- Lowest power consumption at 25 Msps in the LTC2263/4/5-14 family （vs LTC2264CUJ-14)
- 14-bit resolution upgrade path from 12-bit without PCB rework （vs LTC2263CUJ-12)
- Pin-compatible upgrade path to higher sample rates in same family （vs LTC2260CUJ-14)
設計ノート
The LTC2263CUJ-14 datasheet mandates a multilayer PCB with a clean, unbroken ground plane and the first internal layer dedicated to ground directly beneath the ADC. Route the differential analog inputs (VA+/VA-, VB+/VB-) as tightly-coupled 100-ohm differential pairs from the input driver to the ADC pins, keeping trace lengths matched within 0.5 mm to preserve 73.7 dB SNR. Place the 1.8 V AVDD decoupling network (10 uF bulk + 0.1 uF + 1 nF ceramic) within 5 mm of the AVDD pins, and isolate analog and digital ground returns until they join at a single point beneath the exposed paddle.
Each LVDS output pair must be terminated with a 100-ohm differential termination resistor placed close to the receiving FPGA/ASIC pins. Keep the LVDS trace lengths matched within 2 mm to avoid skew-induced sampling errors, and route LVDS away from any analog input traces to prevent digital switching noise from coupling into the 800 MHz input signal path. If using the 1-lane mode, the unused LVDS pairs should be left open or terminated at the receiver; do not float them adjacent to sensitive analog traces.
Do not assume the LTC2263CUJ-12 is interchangeable in software - although the pinout is identical, the output word width and expected data format differ because of the 12-bit vs 14-bit resolution. Ensure your downstream FPGA/ASIC handles the configured 1-lane or 2-lane output mode correctly, as data bits are reassigned between modes. The MODE pin and SPI configuration register both influence this; verify both before assuming output bit positions. Finally, do not exceed the 1.8 V absolute-maximum rating on any supply pin - the part is not 3.3 V tolerant.
コンプライアンス情報
RoHS compliant per manufacturer datasheet (22654314fb). Commercial grade (0C to +70C); not AEC-Q100 qualified for automotive. The #PBF suffix denotes lead-free / RoHS compliant finish.
