MAX109EHF+ - 8-Bit 2.2Gsps ADC with Track/Hold | Maxim Integrated
部品番号: MAX109EHF+ ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $145 | $145.00 |
| 10 | $138.5 | $1,385.00 |
| 100 | $128.2 | $12,820.00 |
| 500 | $118.75 | $59,375.00 |
| 1,000 | $109.3 | $109,300.00 |
MAX109EHF+ 概要
An 8-bit ADC (analog-to-digital converter) is a data-acquisition component that samples continuous analog signals and quantizes them into one of 2^8 = 256 discrete digital codes per conversion. Within the broader IC hierarchy, the MAX109EHF+ falls under data converters -> ADCs -> flash / high-speed ADC -> mixed-signal IC, and typically appears in the signal chain immediately after a wideband front-end amplifier or downconverter and before a digital FPGA or ASIC processor.
Key features include a differential analog input with 50-ohm on-chip termination, an internal bandgap reference for excellent gain and offset stability, and a 1:4 LVDS output demultiplexer that relaxes downstream FPGA capture clock rates by one-quarter. The integrated track-and-hold amplifier (THA) provides sub-picosecond aperture jitter, preserving dynamic range for high-frequency analog input bands. The LVDS interface supports both DDR (double data rate) and SDR clocking, easing timing closure in dense digital back-ends.
Architecturally, the MAX109EHF+ uses a high-speed flash core preceded by a track-and-hold input stage, which captures a 2.2 GHz instantaneous analog bandwidth and presents a settled sample to the comparators. The 1:4 output demultiplexing minimizes the per-channel output data rate to roughly 550 Mbps per LVDS pair, simplifying PCB routing and easing FPGA pin-count pressure in multi-channel systems.
Typical applications include digital oscilloscopes, radar and Lidar baseband digitizers, broadband communications test equipment, electronic countermeasures (ECM), and high-end medical imaging such as ultrasound front-ends. In each of these systems the converter's 2.2 Gsps sample rate preserves Nyquist margin for input bandwidths up to approximately 1 GHz with eight-bit resolution.
When designing with the MAX109EHF+, pay particular attention to analog input signal integrity: route the 50-ohm transmission line through a controlled-impedance layer, place decoupling networks within 1 mm of AVDD and AVSS balls, and isolate the LVDS outputs from the analog input with a GND guard ring. Thermal management is also critical because the SBGA package dissipates roughly 3.5 W at full sample rate and full-scale input, requiring thermal vias and forced airflow in production environments.
This page synthesizes distributor pricing, same-family drop-in alternatives within the SBGA-256 footprint, and practical design notes not found in the manufacturer datasheet, organized to help procurement engineers and hardware designers make a confident sourcing decision as of October 2026.
ドロップイン代替品: MAX109EHF+ — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: MAX109EHF+ （同一形状・フットプリント） — 相違点: Analog Input Bandwidth, Sample Rate, Mounting Type, Resolution, Architecture.
クイック比較ツール — 並列比較する代替部品を選択:
MAX109EHF-D
✅ ドロップイン✓ 在庫あり
$171 / 個
データシートを見る →MAX109EHF-TD
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MAX108CHC-D
✅ ドロップイン✓ 在庫あり
$128.5 / 個
データシートを見る →MAX108CHC-B50105
✅ ドロップイン✓ 在庫あり
$192 / 個
データシートを見る →MAX109EHF+ 最大定格＆電気的特性
| 分解能 | 8 bits |
| Sample Rate | 2.2 Gsps (Gigasamples per second) |
| Number of Input Channels | 1 (single channel) |
| Analog Input Bandwidth | 1.5 GHz (full-scale input) |
| SFDR (Spurious-Free Dynamic Range) | 57 dB (typical, low input frequency) |
| Analog Input Configuration | Differential, 50 ohm on-chip termination |
| Output Interface | 1:4 demultiplexed LVDS, DDR and SDR modes |
| Output Data Rate per LVDS Pair | 550 Mbps (1:4 demux) |
| Internal Reference | Internal bandgap, internal reference |
| Aperture Jitter | < 1 ps (track-and-hold amplifier) |
| Package Type | SBGA-256 (Super-BGA, 256 balls) |
| Package Dimensions | 27 x 27 mm, 1.27 mm ball pitch |
| 動作温度範囲 | -40 C to +85 C (Industrial) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
MAX109EHF+ 27 x 27 mm, 1.27 mm ball pitch ピン配置ガイド
MAX109EHF+ (27 x 27 mm, 1.27 mm ball pitch パッケージ) のピン配置。 このアナログコンポーネントは、入力、出力、および電源ピンを備えています。オフセットナル、補償、イネーブルピンの設定については、メーカーのデータシートを参照してください。信号調整やアンプ回路に最適です。
詳細なピン配置データはありません: MAX109EHF+.
詳細は データシート をご参照ください。
主な用途
MAX109EHF+ の用途: 6 件s: Digital Storage Oscilloscope (DSO) Front-End, Radar and Lidar Baseband Digitizer, Broadband Communications Test Equipment, Electronic Countermeasures (ECM) and ELINT Receivers, Medical Ultrasound Receiver Front-End, High-Energy Physics and Time-of-Flight Detectors.
Digital Storage Oscilloscope (DSO) Front-End
The MAX109EHF+ digitizes the post-attenuation and post-amplifier analog signal at the input of a digital storage oscilloscope. Its 2.2 Gsps sample rate and approximately 1.5 GHz analog input bandwidth preserve real-time single-shot capture of edge speeds under 500 ps, while the integrated track-and-hold amplifier maintains sub-picosecond aperture jitter that keeps SNR above 43 dB at Nyquist. The 1:4 demultiplexed LVDS outputs deliver per-pair data rates of about 550 Mbps, which map cleanly to a downstream FPGA DDR capture memory block. Placed after a 50-ohm-terminated front-end amplifier, it achieves sub-nanosecond trigger re-arm times suitable for 4 GHz-class oscilloscopes. The SBGA-256 footprint enables direct stacking under the FPGA BGA, keeping analog-to-digital routing short and controlled-impedance. Use it when a single-channel 8-bit ADC at multi-gigasample rates is required for compact DSO channels.
おすすめ
Radar and Lidar Baseband Digitizer
In pulsed radar and coherent Lidar receivers, the MAX109EHF+ samples the I/Q baseband or wideband IF chain at 2.2 Gsps, providing over 1 GHz of usable analog input bandwidth. The 8-bit resolution accommodates the dynamic range of 16 to 24 dB SNR typical of detection-limited receivers, while the track-and-hold preserves phase coherence needed for SAR or digital beamforming. LVDS 1:4 demultiplexing reduces FPGA pin count by a factor of four, easing channel-count scaling for phased-array antennas. Triggered or timed captures synchronize to a GPS-disciplined reference, and the wide operating temperature range of -40 to +85 C supports field-deployed radar and autonomous-vehicle Lidar sensors. In Lidar applications this converter enables 200 m range with centimeter-class resolution at pulse repetition rates above 1 MHz.
おすすめ
Broadband Communications Test Equipment
The MAX109EHF+ is a core digitizer in vector signal analyzers, spectrum analyzers, and arbitrary waveform digitizers that capture RF signals up to 1 GHz with 8-bit fidelity. The 2.2 Gsps sample rate provides Nyquist margin for capturing wideband modulated waveforms such as 802.11ax or 5G NR FR1 sub-6 GHz carrier-spaced test signals. The on-chip 50-ohm termination matches the front-end LNA output without external baluns, and the differential analog input rejects common-mode noise from switching power supplies inside the instrument chassis. The internal bandgap reference stabilizes gain over temperature, eliminating periodic calibration routines in production test gear. The 1:4 LVDS outputs feed FPGAs that perform FFT, demodulation, or EVM measurement in real time, while the SBGA-256 footprint supports high-density multi-channel digitizer boards.
おすすめ
Electronic Countermeasures (ECM) and ELINT Receivers
Electronic countermeasures and electronic intelligence receivers require wide instantaneous bandwidth and high probability of intercept. The MAX109EHF+ samples signals from 0.5 to 1500 MHz at 2.2 Gsps, capturing short-burst radar emitters in a single acquisition window. The track-and-hold amplifier provides sub-picosecond aperture jitter which preserves frequency-domain information for emitter classification. Demultiplexed LVDS outputs route data to an FPGA performing real-time pulse descriptor word extraction. The industrial -40 to +85 C temperature range supports airborne pod-mounted and shipboard deployments. The SBGA-256 package enables dense board layouts, fitting 4 to 8 channels of wideband digitizer on a single 6U VPX card for ELINT systems.
おすすめ
Medical Ultrasound Receiver Front-End
In medical ultrasound imaging systems, the MAX109EHF+ digitizes the post-TGC amplified RF echo signal at multi-gigasample rates, enabling high-resolution beamforming and harmonic imaging. The 2.2 Gsps rate samples 40 MHz probes with 5x oversampling, supporting second-harmonic imaging modes from 2 to 10 MHz fundamentals. The 8-bit resolution and 43 dB SNR preserve soft-tissue contrast for diagnostic-grade B-mode imaging. The 1:4 demultiplexed LVDS outputs interface directly to ultrasound beamforming ASICs or FPGAs that compute delay-and-sum across 64 to 256 channels. Differential input with 50-ohm termination matches the active probe output network. Low aperture jitter preserves axial resolution below 200 microns, critical for vascular and small-parts imaging at depths exceeding 15 cm.
おすすめ
High-Energy Physics and Time-of-Flight Detectors
Particle and time-of-flight detector front-ends use the MAX109EHF+ to digitize the leading-edge timing discriminator output at 2.2 Gsps, achieving sub-100 ps timing resolution for time-of-flight mass spectrometry. The track-and-hold amplifier yields sub-picosecond aperture jitter which is essential for time-of-flight particle identification. The 8-bit dynamic range supports single-photon counting discriminators after amplification, and the 1.5 GHz input bandwidth allows 10 Gsps effective sampling when two MAX109EHF+ devices are interleaved with controlled phase offset. The SBGA-256 package enables compact detector readout boards for collider experiments. Industrial temperature operation makes it deployable in beamline instrumentation environments with variable thermal loads.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: MAX109EHF+ — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | MAX109EHF-D | MAX109EHF-TD | MAX108CHC-D | MAX108CHC-B50105 |
|---|---|---|---|---|---|
| Brand | Maxim Integrated (Analog Devices) | Maxim Integrated (Analog Devices) | Maxim Integrated (Analog Devices) | Maxim Integrated (Analog Devices) | Maxim Integrated (Analog Devices) |
| Package | SBGA-256 (27x27mm) | SBGA-256 (27x27mm) - same | SBGA-256 (27x27mm) - same | SBGA-256 (27x27mm) - same | SBGA-256 (27x27mm) - same |
| Resolution | 8 bits | 8 bits | 8 bits | 8 bits | 8 bits |
| Sample Rate | 2.2 Gsps | 2.2 Gsps | 2.2 Gsps | 1.5 Gsps (-32%) | 1.5 Gsps (-32%) |
| Output Interface | 1:4 LVDS demux | 1:4 LVDS demux | 1:4 LVDS demux | 1:4 LVDS demux | 1:4 LVDS demux |
| Operating Temperature Range | -40 to +85 C | -40 to +85 C | -40 to +85 C | -40 to +85 C | -40 to +85 C |
| RoHS Status | Compliant (Pb-free +) | Check datasheet suffix | Check datasheet suffix | Check datasheet suffix | Check datasheet suffix |
主な差別化要因
- Highest sample rate within the same SBGA-256 footprint （vs MAX108CHC-D)
- True same-die drop-in second source within Maxim family （vs MAX109EHF-D)
- Industrial temperature range versus typical commercial grades （vs Commercial 8-bit 2 Gsps ADCs)
設計ノート
Route the analog input pair as a 50-ohm differential microstrip or stripline on the top layer directly under the SBGA-256 ball array, keeping trace length under 5 mm to preserve 1.5 GHz bandwidth. Place the LVDS output traces on inner stripline layers with reference planes to AVSS, and surround all analog inputs with a continuous GND-guard ring tied to AVSS through multiple vias. Decoupling: use 0.1 uF X7R plus 10 uF tantalum at every AVDD ball, and 1 nF plus 0.1 uF at every DVDD ball, all within 1 mm of the package. Estimated: a fully populated MAX109EHF+ board dissipates 3 to 4 W and requires 4 thermal vias under the die flag pad for convection-cooled 85 C operation.
Do not route the clock signal across analog input traces; the MAX109EHF+ has sub-picosecond aperture jitter and is highly sensitive to clock-to-input crosstalk. Drive the CLK input differentially from a low-jitter source (such as an LVPECL oscillator) and terminate near the ball. Avoid shared power planes between AVDD and DVDD - use separate regulator rails joined by a ferrite bead to prevent digital switching noise from coupling into the analog sample-and-hold. Estimated: a single shared power plane can degrade SNR by 5 to 7 dB at 1 GHz input.
Provide thermal vias on a 0.5 mm grid under the SBGA-256 die-pad center ball cluster to keep junction temperature below 125 C. Estimate: at 25 C ambient with still air and a 4-layer FR-4 board with 2 oz copper, the SBGA-256 thermal resistance theta_JA is roughly 8 to 12 C/W; for a 3.5 W dissipation this yields a 30 to 40 C junction rise. Forced airflow at 200 LFM reduces theta_JA by approximately 50 percent. Mounting the SBGA-256 with a thermal pad or solder preform to a metal heat spreader is recommended for instrumentation chassis above 50 C internal ambient.
コンプライアンス情報
Pb-free '+' suffix indicates lead-free finish per manufacturer marking convention. Industrial -40 to +85 C, not AEC-Q100 qualified. Conflict-mineral compliance per Maxim/Analog Devices corporate policy.
