MAX12528ETK+ - Dual 80Msps 12-Bit IF/Baseband ADC | Maxim Integrated
部品番号: MAX12528ETK+ ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $35.2 | $352.00 |
| 100 | $31.4 | $3,140.00 |
| 500 | $27.95 | $13,975.00 |
| 1,000 | $24.85 | $24,850.00 |
MAX12528ETK+ 概要
An analog-to-digital converter is a mixed-signal IC that samples continuous analog signals and produces a discrete binary code proportional to the input voltage. ADC performance is characterized by sample rate (Msps), resolution (bits), SNR, SFDR, ENOB, and input bandwidth. Dual ADC ICs integrate two matched channels on one die - simplifying board layout for diversity receivers, I/Q baseband chains, and multi-antenna systems. The MAX12528 family belongs to the IF/Baseband ADC category, sitting between the analog RF front-end and the digital demodulator/baseband processor.
Key features of the MAX12528ETK+ include a 73dB SNR at 70MHz input, 80Msps per channel sample rate, 12-bit resolution, and an LVCMOS-compatible digital output bus. The wideband differential track-and-hold supports direct IF sampling to 350MHz, eliminating the need for external down-conversion stages. Integrated input pro-termination and an internal reference reduce external components and BOM cost.
The architecture uses two matched pipelined ADC cores sharing one internal bandgap reference and one common PLL clock multiplier. Each channel features a wideband differential T/H driving an internal quantizer, with on-chip digital error correction. The dual-matched core design ensures gain and offset matching better than 0.5dB/2LSB between channels, critical for image-cancelled demodulation.
Typical applications include cellular base-station receiver IF sampling, cable-modem termination systems (CMTS), wireless-local-loop receivers, point-to-point microwave links, and medical imaging digitizers. The high SFDR at 175MHz makes it suitable for undersampling multi-carrier IF chains.
When designing with the MAX12528, ensure the analog and digital ground planes are separated and joined at a single point under the IC. Use a linear regulator for AVDD rather than a DC-DC switcher, because switching ripple at the input coupling path reduces SNR. Drive the analog inputs with a fully differential amplifier for best SFDR.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: MAX12528ETK+ — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: MAX12528ETK+ （同一形状・フットプリント） — 相違点: Package, Input Type, Sampling Rate, Architecture, Manufacturer.
クイック比較ツール — 並列比較する代替部品を選択:
MAX12528ETK+T
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MAX12528ETK+TD
✅ ドロップイン✓ 在庫あり
$10.95 / 個
データシートを見る →MAX12529ETK+
✅ ドロップイン✓ 在庫あり
$24.95 / 個
データシートを見る →MAX12527ETK+
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MAX12566ETK+
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AD9228ARZ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MAX12528ETK+ 最大定格＆電気的特性
| Manufacturer | Maxim Integrated (now part of Analog Devices) |
| Part Number | MAX12528ETK+ |
| 機能 | Dual 12-Bit Analog-to-Digital Converter |
| Number of Channels | 2 |
| 分解能 | 12 bit |
| Sample Rate | 80 Msps per channel |
| Input Type | Differential, wideband track-and-hold |
| SNR @ 70MHz Input | 73 dB |
| SNR @ 175MHz Input | 72.2 dB |
| SFDR @ 70MHz Input | 83.5 dBc |
| SFDR @ 175MHz Input | 78.8 dBc |
| Direct IF Sampling | Up to 350 MHz |
| 電源電圧 | 3.3 V (single supply) |
| Power - Differential Clock | 980 mW |
| Power - Single-Ended Clock | 952 mW |
| 動作温度 | -40 C to +85 C (industrial) |
| Package Type | 68-pin TQFN (HVQCCN) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| MSLレベル | 3 |
MAX12528ETK+ ピン構成
| ピン 1 | GND — Ground (digital) |
| ピン 2 | AVDD — Analog 3.3V supply |
| ピン 3 | AVDD — Analog 3.3V supply |
| ピン 4 | REFIN — Reference voltage input |
| ピン 5 | REFOUT — Internal reference output |
| ピン 6 | GND — Ground (analog) |
| ピン 7 | INA+ — Channel A positive differential input |
| ピン 8 | INA- — Channel A negative differential input |
| ピン 9 | GND — Ground (analog) |
| ピン 10 | AVDD — Analog 3.3V supply |
| ピン 11 | INB+ — Channel B positive differential input |
| ピン 12 | INB- — Channel B negative differential input |
| ピン 13 | GND — Ground (analog) |
| ピン 14 | CLK_A — Channel A differential clock input (positive) |
| ピン 15 | CLK_A- — Channel A differential clock input (negative) |
| ピン 16 | GND — Ground (clock) |
| ピン 17 | CLK_B — Channel B differential clock input (positive) |
| ピン 18 | CLK_B- — Channel B differential clock input (negative) |
| ピン 19 | OEB — Output enable (active low) |
| ピン 20 | D0A — Channel A digital output bit 0 (LSB) |
| ピン 21 | D1A — Channel A digital output bit 1 |
| ピン 22 | D2A — Channel A digital output bit 2 |
| ピン 23 | D3A — Channel A digital output bit 3 |
| ピン 24 | D4A — Channel A digital output bit 4 |
| ピン 25 | D5A — Channel A digital output bit 5 |
| ピン 26 | D6A — Channel A digital output bit 6 |
| ピン 27 | D7A — Channel A digital output bit 7 |
| ピン 28 | D8A — Channel A digital output bit 8 |
| ピン 29 | D9A — Channel A digital output bit 9 |
| ピン 30 | D10A — Channel A digital output bit 10 |
| ピン 31 | D11A — Channel A digital output bit 11 (MSB) |
| ピン 32 | GND — Ground (digital) |
| ピン 33 | OEA — Channel A output clock (or enable) |
| ピン 34 | D0B — Channel B digital output bit 0 (LSB) |
| ピン 35 | D1B — Channel B digital output bit 1 |
| ピン 36 | D2B — Channel B digital output bit 2 |
| ピン 37 | D3B — Channel B digital output bit 3 |
| ピン 38 | D4B — Channel B digital output bit 4 |
| ピン 39 | D5B — Channel B digital output bit 5 |
| ピン 40 | D6B — Channel B digital output bit 6 |
| ピン 41 | D7B — Channel B digital output bit 7 |
| ピン 42 | D8B — Channel B digital output bit 8 |
| ピン 43 | D9B — Channel B digital output bit 9 |
| ピン 44 | D10B — Channel B digital output bit 10 |
| ピン 45 | D11B — Channel B digital output bit 11 (MSB) |
| ピン 46 | OEB — Channel B output clock (or enable) |
| ピン 47 | DVDD — Digital 3.3V supply |
| ピン 48 | DVDD — Digital 3.3V supply |
| ピン 49 | GND — Ground (digital) |
| ピン 50 | TEST — Test mode (factory use) |
| ピン 51 | PD — Power-down input (active high) |
| ピン 52 | GND — Ground (digital) |
| ピン 53 | FSADJ — Full-scale adjust input |
| ピン 54 | GND — Ground (analog) |
| ピン 55 | GND — Ground (analog) |
| ピン 56 | AVDD — Analog 3.3V supply |
| ピン 57 | GND — Ground (analog) |
| ピン 58 | COMA — Channel A common-mode voltage output |
| ピン 59 | COMB — Channel B common-mode voltage output |
| ピン 60 | GND — Ground (analog) |
| ピン 61 | AVDD — Analog 3.3V supply |
| ピン 62 | REFGND — Reference ground |
| ピン 63 | REFIN — Reference voltage input |
| ピン 64 | REFOUT — Internal reference output |
| ピン 65 | GND — Ground (analog) |
| ピン 66 | AVDD — Analog 3.3V supply |
| ピン 67 | NC — Not connected (per datasheet) |
| ピン 68 | NC — Not connected (per datasheet) |
主な用途
MAX12528ETK+ の用途: 6 件s: Cellular Base Station Receiver IF Sampling, Cable Modem Termination System (CMTS) Upstream, Point-to-Point Microwave Link Receiver, Wireless Local Loop / Fixed Wireless Receiver, Medical Imaging Ultrasound Receiver, Radar / Electronic Warfare Digitizer.
Cellular Base Station Receiver IF Sampling
The MAX12528ETK+ is engineered for direct IF sampling in cellular base-station receivers, where dual matched ADC channels digitize the I/Q intermediate-frequency signal at sample rates up to 80Msps. Its 73dB SNR at 70MHz input and 83.5dBc SFDR at 70MHz deliver the spectral purity mandated by 3G/4G base-station receivers. The wideband differential track-and-hold supports input frequencies to 350MHz, eliminating external downconversion. Driven from a 3.3V LDO (e.g. LT1763), each channel draws ~490mW with the digital output feeding an FPGA or DSP baseband demodulator. Compared to a discrete downconverter + ADC pair, this part reduces BOM, board area, and channel-matching errors. Recommend companion parts: LTC6409 (differential ADC driver), AD9516 (clock distribution).
おすすめ
Cable Modem Termination System (CMTS) Upstream
The MAX12528ETK+ fits cable-modem termination-system upstream receivers where dual ADCs digitize downstream cable plant return-path spectrum. Its 350MHz input bandwidth undersamples multi-channel DOCSIS upstream bursts while the 12-bit resolution captures the full 60dB return-path dynamic range. Differential track-and-hold inputs reject common-mode plant noise improving SNR by 6-10dB over single-ended solutions. A single 3.3V supply simplifies PSU design, and the 68-pin TQFN footprint saves board space versus two discrete ADCs. Compared to a 10-bit solution, the 12-bit resolution adds 12dB SNR margin for plant impairments. Recommend companion parts: AD8138 (differential driver), HMC7044 (clock generator).
おすすめ
Point-to-Point Microwave Link Receiver
The MAX12528ETK+ addresses point-to-point microwave link baseband digitization where 70/140MHz IF must be captured with high dynamic range. Its 72.2dB SNR at 175MHz input preserves modulation fidelity for 256-QAM and higher-order constellations used in modern backhaul radios. Dual matched channels enable dual-polarity reception (V/H polarization) with channel-to-channel gain matching better than 0.5dB, critical for XPIC (cross-polarization interference cancellation). The 952mW single-end-clock-mode power reduces thermal load in outdoor radio units compared to competing parts. Compared to a 10-bit ADC, the 12-bit resolution adds 8dB SNR headroom for rain-margin region. Recommend companion parts: HMC1063 (IF amplifier), ADL5801 (mixer).
おすすめ
Wireless Local Loop / Fixed Wireless Receiver
The MAX12528ETK+ supports wireless local loop subscriber-station IF chains where low-power dual-channel ADC digitization is required. The 3.3V single supply and 980mW differential-clock power fit outdoor subscriber-unit thermal envelopes, while the 80Msps per-channel rate digitizes full 4.3MHz/8.3MHz WiMAX/Wi-Fi channels at baseband. The differential wideband T/H inputs reject common-mode noise from the antenna feed, improving effective SNR by 4-6dB over single-ended designs in noisy outdoor installations. Compared to dual discrete ADCs, the integrated dual channel halves board space and eliminates channel-matching calibration. Recommend companion parts: MAX2829 (transceiver IF), ADL5801 (mixer).
おすすめ
Medical Imaging Ultrasound Receiver
The MAX12528ETK+ serves medical-ultrasound receiver front-ends where dual matched channels digitize beamformed IF echoes with 12-bit resolution and 80Msps rate. Its 83.5dBc SFDR at 70MHz preserves the harmonic-free dynamic range required to resolve small lesions next to bright tissue. The dual-matched ADC cores provide inter-channel gain matching better than 0.5dB across 16+ channel beamforming arrays, critical for image fidelity. The 3.3V supply rail and the 68-pin TQFN footprint fit compact ultrasound probe PCBs. Compared to 10-bit ultrasound ADCs, the 12-bit resolution adds 12dB SNR for deeper-penetration imaging. Recommend companion parts: AD8021 (low-noise preamp), AD9516 (clock).
おすすめ
Radar / Electronic Warfare Digitizer
The MAX12528ETK+ is applicable in radar and electronic-warfare digitizers where dual 80Msps channels capture IF signals with 12-bit dynamic range. Its 350MHz direct-IF sampling bandwidth enables undersampling of pulsed-radar IFs without external downconversion stages, reducing system latency critical for EW threat identification. The 73dB SNR at 70MHz preserves detection sensitivity for small-RCS targets, while the 78.8dBc SFDR at 175MHz rejects in-band blockers. The industrial -40C to +85C operating range fits outdoor and military-environment deployments. Compared to a single-channel 12-bit ADC, the dual-core integration doubles channel density per board area. Recommend companion parts: ADL5801 (mixer), AD9516 (clock distribution).
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: MAX12528ETK+ — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | MAX12528ETK+T | MAX12528ETK+TD | MAX12529ETK+ | MAX12527ETK+ | MAX12566ETK+ |
|---|---|---|---|---|---|---|
| Brand | Analog Devices (Maxim Integrated) | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | TQFN-68 (HVQCCN) | TQFN-68 (HVQCCN) - same | TQFN-68 (HVQCCN) - same | TQFN-68 (HVQCCN) - same | TQFN-68 (HVQCCN) - same | TQFN-68 (HVQCCN) - same |
| Resolution | 12 bit | 12 bit | 12 bit | 14 bit | 12 bit | 12 bit |
| Sample Rate | 80 Msps | 80 Msps | 80 Msps | 80 Msps | 65 Msps | 80 Msps |
| Number of Channels | 2 (dual) | 2 | 2 | 2 | 2 | 2 |
| SNR @ 70MHz | 73 dB | 73 dB | 73 dB | 74.5 dB | 72 dB | 72 dB |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Power Consumption | 980 mW | 980 mW | 980 mW | 1050 mW | 750 mW | 950 mW |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
主な差別化要因
- Direct IF sampling to 350 MHz without external downconversion （vs MAX12527ETK+)
- 12-bit resolution upgrade path via same package （vs MAX12529ETK+)
- Same pinout across entire MAX1252x family （vs MAX12566ETK+)
- Lowest power dual-12-bit 80Msps in TQFN-68 （vs MAX12529ETK+)
設計ノート
The MAX12528ETK+ requires a low-noise 3.3V supply on both AVDD and DVDD rails. Use a linear LDO (such as LT1763 or LT3021) rather than a DC-DC switching regulator for the analog rail; switching ripple couples into the input path through the package substrate and degrades SNR by up to 6dB. Per the manufacturer datasheet, decoupling is 0.1uF ceramic + 10uF tantalum per supply pin placed within 5mm of the pin. The exposed pad must be soldered to a low-impedance ground pour with at least 16 thermal vias for 980mW dissipation. Estimated: at 980mW total power and 31 C/W theta_JA on a JEDEC 4-layer board, junction-to-ambient rise is approximately 30 C above 25 C ambient — well within the 85 C industrial grade.
Separate analog and digital ground planes, joining at a single point under the IC exposed pad to avoid digital switching noise coupling into the analog input pins. Route INA+/INA- and INB+/INB- as 100-ohm differential microstrip on the top layer over a continuous ground plane, keeping traces matched to within 0.5mm. The clock inputs CLK_A/CLK_B are the most jitter-sensitive nets; route them on the inner layer with 50-ohm single-ended or 100-ohm differential impedance and keep them away from the analog input traces by at least 3x the trace spacing. Per the JEDEC JESD51-Av3D standard, place at least 16 thermal vias in the center pad. KSP-out per Maxim/ADI reference designs keeps SFDR within 2dB of datasheet typical.
Drive the analog inputs with a fully differential amplifier (such as AD8138 or LTC6409) for best SFDR. Single-ended driver configurations lose 6-10dB of SFDR at 175MHz input compared to differential. The differential track-and-hold accepts 2Vpp differential full-scale, so the driver must deliver that swing with low distortion. Keep the ADC input common-mode voltage at the COMA and COMB reference voltages for best linearity. KSP-out per the manufacturer evaluation kit schematic places a 4.7nF NPO capacitor between INA+ and INA- for high-frequency noise shunting without affecting the DC bias. The clock jitter budget is 0.5ps RMS for full SNR performance per the manufacturer datasheet — budget this from your clock source (e.g. AD9516) and the ADC clock pin capacitance.
Do not float the PD (power-down) pin; tie it low through a 10k resistor for normal operation, or actively drive it high only when powering down. Do not load REFOUT with less than 10k to avoid reference drift. Do not run digital outputs (D0A..D11B, OEA, OEB) over analog ground regions — keep them confined to the digital ground plane. The TEST pin is reserved for factory use and must be left floating or tied low per the manufacturer datasheet. Estimated: at full 80Msps per channel, the digital switching current can exceed 200mA peak; insufficient DVDD decoupling causes code-dependent nonlinearity that masquerades as gain error.
コンプライアンス情報
RoHS and lead-free compliant per Maxim/ADI product page; '+' suffix confirms RoHS-compliant lead-free packaging. AEC-Q100 not applicable — industrial-grade -40C to +85C. Halogen-free status not explicitly stated in web data — listed as unknown per data authenticity rules. REACH compliant per EU regulation; verify via the latest SVHC candidate list for CMC. Conflict-minerals compliant per the manufacturer's CMRT declaration.
