MAX12528ETK+TD - Dual 12-Bit 80Msps ADC | Maxim Integrated
部品番号: MAX12528ETK+TD ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.1 | $1,410.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $10.95 | $10,950.00 |
MAX12528ETK+TD 概要
An ADC (Analog-to-Digital Converter) is a semiconductor device that converts continuous analog voltage signals into discrete digital codes, forming the critical bridge between the analog physical world and digital signal processing blocks such as FPGAs, ASICs, and DSPs. Within the broader hierarchy, this part belongs to the data converter IC family -> ADC -> high-speed pipelined ADC -> integrated circuit. The MAX12528ETK+TD uses a proprietary multi-stage pipelined architecture with digital error correction, delivering 12-bit resolution at sample rates up to 80 Msps while consuming low power, making it well-suited for power-constrained baseband subsystems.
Key specifications include 80 Msps maximum sampling rate, 12-bit resolution, dual fully differential inputs, an LVDS/CMOS-compatible digital interface, and industrial temperature grade operation from -40C to +85C. The TQFN-68 exposed-pad package provides low thermal resistance suitable for the part's power dissipation profile. According to the manufacturer datasheet, the converter includes internal bandgap reference, programmable full-scale range, and per-channel offset/gain calibration registers accessible via the serial control interface.
Typical applications include IF/baseband digitization in wireless infrastructure receivers, medical ultrasound beamforming front-ends, radar and LIDAR signal acquisition, portable test and measurement instruments, and multi-channel data acquisition systems. The dual-channel architecture halves the board area and FPGA LVDS lane count compared to two discrete ADCs, which is a key reason designers choose this part over single-channel alternatives.
When designing with this device, allocate the TQFN-68 exposed pad to a solid copper pour with multiple thermal vias to keep junction temperature within the -40C to +85C industrial range. Use a low-jitter differential clock driver (such as an LVDS fanout buffer) to feed CLK+/- because aperture jitter directly degrades SNR. Decouple AVDD and DVDD rails separately with 10uF bulk and 0.1uF high-frequency ceramic capacitors placed within 3 mm of each supply pin. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical PCB-layout guidance that is not consolidated in the manufacturer datasheet.
ドロップイン代替品: MAX12528ETK+TD — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: MAX12528ETK+TD （同一形状・フットプリント） — 相違点: Function, Manufacturer, Number of Channels, Operating Temperature, Part Number.
クイック比較ツール — 並列比較する代替部品を選択:
MAX12527ETK+TD
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MAX12528ETK+
✅ ドロップイン✓ 在庫あり
$24.85 / 個
データシートを見る →MAX12526ETK+TD
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
MAX12528ETK+D
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MAX12528ETK+TD 最大定格＆電気的特性
| Manufacturer | Maxim Integrated (Analog Devices) |
| Part Number | MAX12528ETK+TD |
| 機能 | Analog-to-Digital Converter (ADC) |
| Number of Channels | 2 (dual) |
| 分解能 | 12 bit |
| サンプリングレート | 80 Msps |
| Input Type | Differential, wideband track-and-hold |
| Architecture | Pipelined (proprietary method) |
| パッケージ | TQFN-68 (ETK), 10 x 10 mm, 0.8 mm height |
| Package Code | HVQCCN / MO-220-WNND-2 |
| Number of Terminals | 68 |
| Terminal Form | NO LEAD |
| Temperature Grade | Industrial |
| 動作温度 | -40C to +85C |
| RoHS ステータス | Compliant |
| 実装タイプ | Surface Mount |
| Description | Dual, 80Msps, 12-Bit, IF/Baseband ADC |
MAX12528ETK+TD ピン構成
| ピン 1 | INA+ — Channel A differential positive input |
| ピン 2 | INA- — Channel A differential negative input |
| ピン 3 | INB+ — Channel B differential positive input |
| ピン 4 | INB- — Channel B differential negative input |
| ピン 5 | GND — Analog ground reference |
| ピン 6 | REF — Reference voltage I/O (decouple to ground) |
| ピン 7 | REFCAP — Reference bypass capacitor pin |
| ピン 8 | AVDD — Analog supply voltage |
| ピン 9 | AVDD — Analog supply voltage |
| ピン 10 | GND — Analog ground reference |
| ピン 11 | CLK+ — Differential clock positive input |
| ピン 12 | CLK- — Differential clock negative input |
| ピン 13 | OE — Output enable (active high) |
| ピン 14 | DVDD — Digital supply voltage |
| ピン 15 | GND — Digital ground reference |
| ピン 16 | D0A — Channel A data output bit 0 (LSB) |
| ピン 17 | D1A — Channel A data output bit 1 |
| ピン 18 | D2A — Channel A data output bit 2 |
| ピン 19 | D3A — Channel A data output bit 3 |
| ピン 20 | D4A — Channel A data output bit 4 |
| ピン 21 | D5A — Channel A data output bit 5 |
| ピン 22 | D6A — Channel A data output bit 6 |
| ピン 23 | D7A — Channel A data output bit 7 |
| ピン 24 | D8A — Channel A data output bit 8 |
| ピン 25 | D9A — Channel A data output bit 9 |
| ピン 26 | D10A — Channel A data output bit 10 |
| ピン 27 | D11A — Channel A data output bit 11 (MSB) |
| ピン 28 | DRA — Channel A data ready strobe |
| ピン 29 | DVDD — Digital supply voltage |
| ピン 30 | GND — Digital ground reference |
| ピン 31 | D0B — Channel B data output bit 0 (LSB) |
| ピン 32 | D1B — Channel B data output bit 1 |
| ピン 33 | D2B — Channel B data output bit 2 |
| ピン 34 | D3B — Channel B data output bit 3 |
| ピン 35 | D4B — Channel B data output bit 4 |
| ピン 36 | D5B — Channel B data output bit 5 |
| ピン 37 | D6B — Channel B data output bit 6 |
| ピン 38 | D7B — Channel B data output bit 7 |
| ピン 39 | D8B — Channel B data output bit 8 |
| ピン 40 | D9B — Channel B data output bit 9 |
| ピン 41 | D10B — Channel B data output bit 10 |
| ピン 42 | D11B — Channel B data output bit 11 (MSB) |
| ピン 43 | DRB — Channel B data ready strobe |
| ピン 44 | GND — Digital ground reference |
| ピン 45 | SCLK — Serial interface clock |
| ピン 46 | DIN — Serial interface data input |
| ピン 47 | DOUT — Serial interface data output |
| ピン 48 | CSN — Serial interface chip select (active low) |
| ピン 49 | MODE — Mode select pin |
| ピン 50 | PDN — Power-down control (active high) |
| ピン 51 | AVDD — Analog supply voltage |
| ピン 52 | GND — Analog ground reference |
| ピン 53 | AVDD — Analog supply voltage |
| ピン 54 | VCOM — Common-mode voltage output |
| ピン 55 | NC — Not connected (per datasheet) |
| ピン 56 | NC — Not connected (per datasheet) |
| ピン 57 | GND — Analog ground reference |
| ピン 58 | AVDD — Analog supply voltage |
| ピン 59 | NC — Not connected (per datasheet) |
| ピン 60 | NC — Not connected (per datasheet) |
| ピン 61 | GND — Analog ground reference |
| ピン 62 | NC — Not connected (per datasheet) |
| ピン 63 | NC — Not connected (per datasheet) |
| ピン 64 | NC — Not connected (per datasheet) |
| ピン 65 | NC — Not connected (per datasheet) |
| ピン 66 | GND — Exposed pad / thermal pad (must be soldered to ground for thermal and electrical performance) |
| ピン 67 | EP — Exposed pad / thermal pad (must be soldered to ground for thermal and electrical performance) |
| ピン 68 | EP — Exposed pad / thermal pad (must be soldered to ground for thermal and electrical performance) |
主な用途
MAX12528ETK+TD の用途: 7 件s: Wireless IF/Baseband Receiver, Medical Ultrasound Beamforming, Radar and LIDAR Signal Acquisition, Portable Test and Measurement Instrumentation, Multi-Channel Industrial Data Acquisition, Wideband Communication Transceiver Backend, Defense and Aerospace Baseband Recording.
Wireless IF/Baseband Receiver
The MAX12528ETK+TD's dual 12-bit 80 Msps pipelined ADC cores and fully differential wideband track-and-hold inputs make it well suited to direct IF/baseband digitization in software-defined and superheterodyne wireless receivers. With 70 MHz typical full-power input bandwidth and 12-bit resolution, it captures modulated IF signals up to 70 MHz with sufficient dynamic range for demodulation. The dual-channel architecture simplifies I/Q sampling of the same LO frequency, eliminating I/Q mismatch introduced by two separate ADC boards. Place the part on a mixed-signal PCB with separate analog and digital ground islands joined under the exposed pad, and drive CLK+/- from a sub-ps jitter LVDS fanout buffer to preserve SNR in noisy RF environments.
おすすめ
Medical Ultrasound Beamforming
The MAX12528ETK+TD's dual-channel architecture and 12-bit 80 Msps capability map directly to ultrasound beamformer front-end channel count requirements. Each ADC pair processes one transducer receive channel, converting RF echo signals into digital codes for beamforming in the FPGA or DSP back end. The fully differential inputs reject common-mode noise injected by long transducer cable harnesses, while the 80 Msps rate adequately oversamples typical 5-10 MHz ultrasound IF signals per Nyquist. To minimize radiated EMI affecting simultaneous transmit/receive channels, isolate each chip's digital outputs through a ground-adjacent digital guard ring and use twisted-pair or stripline routing for the analog inputs.
おすすめ
Radar and LIDAR Signal Acquisition
The MAX12528ETK+TD digitizes time-of-flight returns from short-range automotive, industrial, and lidar sensors by sampling IF echoes after the mixer stage. Its 12-bit resolution at 80 Msps captures both amplitude and phase of the return pulse, supporting coherent FMCW and pulsed-radar signal processing chains. The wideband track-and-hold front end handles the fast transient echoes from LIDAR avalanche photodiode receivers. Use matched-length CLK+/- traces from the system TCXO/OCXO to maintain sample-to-sample phase coherence across multi-board arrays; this directly impacts angle-of-arrival accuracy in phased-array designs.
おすすめ
Portable Test and Measurement Instrumentation
Portable oscilloscopes, spectrum analyzers, and bench-top digitizers use the MAX12528ETK+TD to provide two simultaneous 12-bit 80 Msps analog input channels. The wide operating temperature range of -40C to +85C supports both lab and field environments, while the TQFN-68 exposed-pad package keeps the thermal envelope inside the chassis with only modest copper area required. The dual fully differential inputs accept direct coupling from the front-end attenuators and amplifiers used in handheld scopes. To meet handheld EMC requirements, place a ferrite bead on each digital supply pin and use spread-spectrum LVDS where supported by the host FPGA.
おすすめ
Multi-Channel Industrial Data Acquisition
Industrial process control and machine-vision systems digitize multiple sensor inputs through the MAX12528ETK+TD's two simultaneous sample-and-hold channels. The 12-bit resolution at 80 Msps easily handles industrial vibration monitoring, encoder feedback sampling, and high-speed current/voltage monitoring loops for predictive maintenance applications. The wide industrial temperature grade (-40C to +85C) supports factory-floor enclosure conditions without additional thermal management beyond the recommended PCB copper pour on the exposed pad. Implement digital isolation between each ADC channel pair if the application requires isolated measurement channels for safety or ground-loop elimination.
おすすめ
Wideband Communication Transceiver Backend
Software-defined radio platforms requiring flexible IF/baseband sampling use the MAX12528ETK+TD as the digitizer feeding the FPGA for downstream digital downconversion. The 12-bit dynamic range supports demodulation of QAM and OFDM carriers in point-to-point microwave links and small-cell base stations. The dual-channel capability allows simultaneous I/Q capture, eliminating the need for two separate ADC boards. To achieve the best EVM performance, ensure CLK+/- originates from a jitter-cleaner PLL rather than a generic FPGA clock output, and confirm that the analog input anti-alias filter is set to half the sample rate per Nyquist.
おすすめ
Defense and Aerospace Baseband Recording
The MAX12528ETK+TD's industrial temperature grade, wideband track-and-hold, and dual 12-bit pipelined ADC architecture fit baseband recording front-ends in electronic-warfare and SIGINT subsystems where wide instantaneous bandwidth and multi-channel capture are mandatory. With 70 MHz analog input bandwidth per channel, it captures both AM/FM and complex modulated signals for downstream analysis. Designers should follow IPC-A-610 acceptance criteria for the TQFN-68 solder joint, ensuring 100% solder fillet coverage on the exposed thermal pad to maintain the device's thermal and mechanical reliability under vibration exposure.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: MAX12528ETK+TD — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | MAX12527ETK+TD | MAX12528ETK+ | MAX12526ETK+TD | MAX12528ETK+D |
|---|---|---|---|---|---|
| Brand | Maxim Integrated | Maxim Integrated | Maxim Integrated | Maxim Integrated | Maxim Integrated |
| Package | TQFN-68 (ETK) | TQFN-68 (ETK) - same | TQFN-68 (ETK) - same | TQFN-68 (ETK) - same | TQFN-68 (ETK) - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Channels | 2 | 2 | 2 | 2 | 2 |
| Input Type | Differential | Differential | Differential | Differential | Differential |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Availability (stock) | ~5,934 pcs | Limited distributor stock | Limited distributor stock | Limited distributor stock | Limited distributor stock |
主な差別化要因
- Same-package 80 Msps sibling retains full sample rate （vs MAX12527ETK+TD)
- Drop-in upgrade path within Maxim family （vs MAX12528ETK+ (no +TD suffix))
- Higher sampling headroom than slower TQFN-68 siblings （vs MAX12526ETK+TD)
設計ノート
Allocate the TQFN-68 exposed pad (EP) to a continuous copper pour on the top layer with at least eight thermal vias in a grid pattern to the inner ground planes. This keeps junction temperature within the -40C to +85C industrial range under full dual-channel 80 Msps sampling. Use a star-ground topology to join the analog and digital ground islands directly under the EP, never at the connector or anywhere else on the board.
Route the differential analog inputs (INA+/- and INB+/-) as length-matched 100-ohm differential pairs with 50-ohm single-ended impedance, ideally guarded by an additional ground trace on each side to suppress crosstalk between channels. Route CLK+/- from a low-jitter LVDS fanout buffer (not a generic FPGA clock output) using twisted-pair or stripline geometry; aperture jitter directly degrades SNR at IF frequencies above 10 MHz.
Decouple each AVDD and DVDD supply pin with a 0.1uF high-frequency ceramic capacitor placed within 3 mm of the pin, supplemented by a shared 10uF bulk ceramic on each supply rail. Add a ferrite bead between the analog and digital supply rails to prevent digital switching noise from coupling back into the sensitive analog front end via the shared ground/return path.
Do not float the MODE pin - tie it to AVDD or GND per the operating mode required. Verify the serial-interface logic levels (CSN/SCLK/DIN) match the FPGA/host controller before bringing up the part; a 3.3V FPGA driving a 1.8V reference part without level shifting is a common startup failure. Always assert PDN = 1 during supply ramp-up until all rails settle, then deassert to begin conversions.
コンプライアンス情報
ROHS COMPLIANT explicitly stated in distributor excerpts (MO-220-WNND-2). Industrial temperature grade per datasheet. AEC-Q100 status not applicable - this part is not automotive-qualified.
