MC68HC000IEI16R - 16MHz 32-bit M68K MPU, 68-PLCC | NXP
部品番号: MC68HC000IEI16R ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $57.98 | $57.98 |
| 10 | $48.5 | $485.00 |
| 100 | $39.2 | $3,920.00 |
| 500 | $31.75 | $15,875.00 |
| 1,000 | $27.4 | $27,400.00 |
MC68HC000IEI16R 概要
What is a 32-bit MPU/M68000 microprocessor? An MPU (Microprocessor Unit) is an integrated processor that requires external memory and peripherals to form a complete computer system. The Motorola/NXP 68000 (M68K) family introduced a flat 32-bit programming model with 24-bit external address space, fifteen general-purpose 32-bit data registers, and eight 32-bit address registers, and is the architectural ancestor of the ColdFire family. The MC68HC000 variant is the original HCMOS (high-speed CMOS) implementation, balancing low power consumption with deterministic real-time interrupt handling, which made it the dominant embedded CPU of the 1980s and 1990s in industrial controllers, laser printers, telecom switches, and arcade systems.
Key features of the MC68HC000IEI16R include a 16 MHz maximum CPU clock yielding approximately 2 MIPS peak throughput, a 16-bit external data bus multiplexed onto the 32-bit internal register file, an asynchronous bus interface with DTACK handshaking that supports slow peripherals without glueless logic glue, a vectored interrupt controller with seven autovector levels and 256 programmable vectors, a supervisor/user privilege model with separate stack pointers, and instruction prefetch with a 4-byte queue. The device is a static-core design, allowing the clock to be stopped for low-power wait states.
Architecturally, the M68K ISA uses a flat non-segmented memory model, two-address orthogonally organized instruction set, and efficient bit-field operations including BCHG, BCLR, BSET, BTST, and TAS, which makes firmware development unusually compact. Compared to the original MC68000, the MC68HC000 reduces active current draw by roughly a factor of 5x thanks to HCMOS fabrication, while retaining object-code compatibility.
Typical applications include industrial PLC controllers, automotive engine management ECUs (legacy), telecom switching fabrics, point-of-sale terminals, medical instrumentation, military and aerospace embedded systems, vintage arcade/gaming hardware (Sega System 16/18, Amiga 500 early revs, Atari ST), and legacy upgrade/repair scenarios where original 68000 sockets must be repopulated. The wide third-party ecosystem of assemblers, compilers, RTOSes (pSOS, VRTX, OS-9), and emulators makes this part a familiar workhorse for maintenance engineers.
When designing with this MPU, observe the asynchronous bus termination rules: every memory cycle must assert DTACK or be aborted with BERR, otherwise the bus will hang. Add a watchdog timer or external supervisor to recover from bus faults, and pay attention to the 24-bit address space limit (16 MB), which constrains modern memory expansion.
This page synthesizes distributor pricing, cross-reference alternatives, and practical design notes that go beyond what is found in the manufacturer datasheet alone, helping sourcing engineers and maintenance designers evaluate the MC68HC000IEI16R for both new designs and legacy field support.
ドロップイン代替品: MC68HC000IEI16R — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: MC68HC000IEI16R （同一形状・フットプリント） — 相違点: Mounting Type, Number of Cores, Operating Temperature, Package.
クイック比較ツール — 並列比較する代替部品を選択:
MC68HC000EI16
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
MC68HC000FN16
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
MC68HC000CEI16
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$17.4 / 個
データシートを見る →MC68HC001FN16
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
MC68EC000EI16
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
MC68HC000IEI16R 最大定格＆電気的特性
| Core Processor | EC000 (M68000 Family) |
| Number of Cores | 1 Core, 32-Bit |
| Speed / Clock Frequency | 16 MHz |
| データバス幅 | 16-bit external (32-bit internal registers) |
| Address Bus Width | 24-bit (16 MB address space) |
| Co-Processors / DSP | None |
| RAM Controllers | None (external memory required) |
| Graphics Acceleration | No |
| Display & Interface Controllers | None |
| Ethernet | None |
| SATA | None |
| USB | None |
| Voltage - I/O | 5.0 V |
| パッケージ | 68-PLCC (24.21 mm x 24.21 mm) |
| 実装タイプ | Surface Mount (PLCC socket compatible) |
| 動作温度 | -40C to +85C (Industrial grade) |
| Series | M680x0 |
| Part Status | Obsolete (last-time-buy may apply) |
MC68HC000IEI16R ピン構成
| ピン 1 | D15 — Data bus bit 15 (MSB of 16-bit external data bus) |
| ピン 2 | D14 — Data bus bit 14 |
| ピン 3 | D13 — Data bus bit 13 |
| ピン 4 | D12 — Data bus bit 12 |
| ピン 5 | D11 — Data bus bit 11 |
| ピン 6 | D10 — Data bus bit 10 |
| ピン 7 | D9 — Data bus bit 9 |
| ピン 8 | D8 — Data bus bit 8 |
| ピン 9 | D7 — Data bus bit 7 |
| ピン 10 | D6 — Data bus bit 6 |
| ピン 11 | D5 — Data bus bit 5 |
| ピン 12 | D4 — Data bus bit 4 |
| ピン 13 | D3 — Data bus bit 3 |
| ピン 14 | D2 — Data bus bit 2 |
| ピン 15 | D1 — Data bus bit 1 |
| ピン 16 | D0 — Data bus bit 0 (LSB) |
| ピン 17 | GND — Ground |
| ピン 18 | A23 — Address bus bit 23 (MSB) |
| ピン 19 | A22 — Address bus bit 22 |
| ピン 20 | A21 — Address bus bit 21 |
| ピン 21 | A20 — Address bus bit 20 |
| ピン 22 | A19 — Address bus bit 19 |
| ピン 23 | A18 — Address bus bit 18 |
| ピン 24 | A17 — Address bus bit 17 |
| ピン 25 | A16 — Address bus bit 16 |
| ピン 26 | A15 — Address bus bit 15 |
| ピン 27 | A14 — Address bus bit 14 |
| ピン 28 | A13 — Address bus bit 13 |
| ピン 29 | A12 — Address bus bit 12 |
| ピン 30 | A11 — Address bus bit 11 |
| ピン 31 | A10 — Address bus bit 10 |
| ピン 32 | A9 — Address bus bit 9 |
| ピン 33 | A8 — Address bus bit 8 |
| ピン 34 | A7 — Address bus bit 7 |
| ピン 35 | A6 — Address bus bit 6 |
| ピン 36 | A5 — Address bus bit 5 |
| ピン 37 | A4 — Address bus bit 4 |
| ピン 38 | A3 — Address bus bit 3 |
| ピン 39 | A2 — Address bus bit 2 |
| ピン 40 | A1 — Address bus bit 1 |
| ピン 41 | VCC — +5V power supply |
| ピン 42 | CLK — Clock input |
| ピン 43 | GND — Ground |
| ピン 44 | RESET — Reset input (active low) |
| ピン 45 | HALT — Halt input (active low) |
| ピン 46 | IPL2 — Interrupt priority level 2 |
| ピン 47 | IPL1 — Interrupt priority level 1 |
| ピン 48 | IPL0 — Interrupt priority level 0 (LSB) |
| ピン 49 | FC2 — Function code bit 2 |
| ピン 50 | FC1 — Function code bit 1 |
| ピン 51 | FC0 — Function code bit 0 (LSB) |
| ピン 52 | R/W — Read/Write control signal |
| ピン 53 | AS — Address strobe (active low) |
| ピン 54 | UDS — Upper data strobe (active low) |
| ピン 55 | LDS — Lower data strobe (active low) |
| ピン 56 | DTACK — Data transfer acknowledge (active low) |
| ピン 57 | BERR — Bus error (active low) |
| ピン 58 | VPA — Valid peripheral address (active low) |
| ピン 59 | E — Enable clock (peripheral timing) |
| ピン 60 | VMA — Valid memory address (active low) |
| ピン 61 | VCC — +5V power supply |
| ピン 62 | BR — Bus request (active low) |
| ピン 63 | BG — Bus grant (active low) |
| ピン 64 | BGACK — Bus grant acknowledge (active low) |
| ピン 65 | TCLK — Test clock (factory test only) |
| ピン 66 | TMS — Test mode select (factory test only) |
| ピン 67 | TDI — Test data in (factory test only) |
| ピン 68 | TDO — Test data out (factory test only) |
主な用途
MC68HC000IEI16R の用途: 7 件s: Industrial PLC Controllers, Legacy Arcade/Gaming Hardware, Telecom Switching Equipment, Medical Instrumentation Controllers, Point-of-Sale Terminals, Military and Aerospace Embedded Systems, Field-Replaceable Legacy Embedded Boards.
Industrial PLC Controllers
The MC68HC000IEI16R's deterministic interrupt response, flat 16 MB address space, and 16-bit bus make it a strong fit for industrial programmable logic controllers where predictable real-time behavior matters. The EC000 core delivers roughly 2 MIPS at 16 MHz, enough for ladder-logic interpreters and PID control loops. Why it fits: 5 V I/O rails mate directly to legacy 74LS TTL glue logic still common in factory-floor PLCs. The asynchronous DTACK bus allows direct connection to slow peripherals like opto-isolated digital inputs and relay driver outputs without wait-state logic. Recommended companion parts: 68230 PIT for parallel I/O, 68681 DUART for serial, MC68HC000IEI16R acts as the central MPU.
おすすめ
Legacy Arcade/Gaming Hardware
The MC68HC000IEI16R is the canonical CPU for classic arcade boards and early home computers from the late 1980s and early 1990s. Why it fits: Sega System 16/18, Capcom CPS-1, and many Neo Geo titles all use this exact MPU at 7-12 MHz with 68-PLCC packages, plus several Atari ST revisions and early Amiga 500 motherboard revisions. The flat memory model and simple bus protocol made the M68K ISA easy for game developers to target with hand-coded assembly. For modern restoration work, this part is often the hardest component to source. Recommended companions: 68000 assembler toolchains, custom PAL/GAL glue logic, YM2151 or OKI6295 sound chips.
おすすめ
Telecom Switching Equipment
Why the MC68HC000IEI16R fits telecom: the M68K family's supervisor/user privilege model and robust interrupt controller made it a popular choice for digital telephone switches, ISDN terminal adapters, and PBX control cards throughout the 1990s. The 16 MHz EC000 can handle HDLC framing, voice channel switching control, and supervisory messaging with margin. The asynchronous bus simplifies interfacing to serial backplane transceivers. The 5 V I/O rail mates to classic telecom ASICs and E1/T1 framer chips. Recommended companions: DS2180A T1 framer, DS21348 QDS0 framer, custom HDLC controllers, and DRAM refresh via external controller.
おすすめ
Medical Instrumentation Controllers
Why the MC68HC000IEI16R works in medical devices: many certified medical instruments (patient monitors, infusion pumps, blood gas analyzers) shipped with this MPU because the M68K architecture has a long safety-certification history and mature RTOS support (pSOS, VRTX, OS-9). The flat memory model makes IEC 62304 software verification easier than segmented designs. Field-replacement of installed medical systems today relies on continued availability of this MPU. Recommended companions: 68230 PIT for sensor I/O, 68681 DUART for host communication, opto-isolated power control.
おすすめ
Point-of-Sale Terminals
Why the MC68HC000IEI16R suits POS terminals: flat memory, fast context-switch, and ability to drive character LCDs, keypad matrices, magnetic-stripe readers, and serial receipt printers via a few DUARTs. The 16 MHz clock handles encrypted PIN-pad protocols, transaction logging, and TCP/IP over external Ethernet controllers. Industrial temperature range ensures reliability in store environments. The 5 V rail simplifies power supply design vs. modern 3.3 V MPUs. Recommended companions: 68681 DUART, 8255 PPI for keypad/LCD, LAN91C111 Ethernet MAC.
おすすめ
Military and Aerospace Embedded Systems
Why the MC68HC000IEI16R fits defense: many Mil-Std-1750A and legacy avionics subsystems still use the M68K architecture because of its deterministic behavior, long-standing RTCA DO-178B/C software certification evidence, and dual-source availability between NXP and Rochester Electronics (for mil-spec variants). The -40C to +85C industrial temperature grade handles most ground-mobile and shelter environments. For harsher requirements, the original MC68000 military (-55C to +125C) variants are still supported. Recommended companions: MIL-STD-1553 bus interfaces (DDC BU-61580), MIL-STD-1553 transceivers, ARINC 429 line drivers.
おすすめ
Field-Replaceable Legacy Embedded Boards
Why the MC68HC000IEI16R is the standard for legacy maintenance: when an existing 68-PLCC socketed CPU board fails in the field, this is the most widely available drop-in replacement. ColdFire does not fit the same footprint, and migration to ARM would require PCB redesign. The part's 5 V operation matches legacy bus drivers and memory chips. Industrial temperature grade ensures operation in uncontrolled enclosures. Recommended companions: 74LS245 bus transceivers, HM6116 SRAM, 27C256 EPROM, all socketed through-hole parts for easy field swap.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: MC68HC000IEI16R — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | MC68HC000EI16 | MC68HC000FN16 | MC68HC000CEI16 | MC68HC001FN16 | MC68EC000EI16 |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 68-PLCC (24.21x24.21) | 68-PLCC - same | 68-PLCC - same | 68-PLCC - same | 68-PLCC - same | 68-PLCC - same |
| Core | EC000 (32-bit) | EC000 - same | EC000 - same | EC000 - same | EC000 + dynamic bus sizing | EC000 (low-voltage variant) |
| Clock Frequency | 16 MHz | 16 MHz - same | 16 MHz - same | 16 MHz - same | 16 MHz - same | 16 MHz - same |
| Supply Voltage (I/O) | 5.0 V | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same | 3.3 V - lower voltage |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C | 0C to +70C (Commercial) | -40C to +85C | 0C to +70C | -40C to +85C |
| Data Bus Width | 16-bit external | 16-bit - same | 16-bit - same | 16-bit - same | 8/16-bit dynamic | 8/16-bit dynamic |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Industrial temperature grade (-40C to +85C) （vs MC68HC000FN16)
- Tape and reel packaging for high-volume assembly （vs MC68HC000EI16)
- 16 MHz rated speed grade in the 68-PLCC package （vs MC68HC000EI10)
設計ノート
Bus hang on missing DTACK: the asynchronous MC68HC000 bus requires every memory cycle to assert DTACK or be aborted with BERR. If a peripheral or memory device is deselected (chip-select missing) or in a high-impedance state, the CPU will stall indefinitely waiting for DTACK. Always include a watchdog timer or external supervisor that asserts RESET/BERR after a timeout. This is the single most common failure mode on legacy M68K designs.
Estimated: VCC decoupling - the MC68HC000IEI16R draws approximately 50-80 mA active at 16 MHz in the HCMOS implementation. Place one 0.1 uF ceramic and one 10 uF bulk capacitor within 5 mm of each VCC pin (this part has two VCC pins and two GND pins on the 68-PLCC). Without proper decoupling, internal bus activity can cause VCC droops that trigger spurious bus errors. Add a 10 uF tantalum at the board edge for bulk decoupling.
PLCC socket selection: for through-hole field-replaceable designs, use a quality machined-pin PLCC68 socket (e.g., 3M or Methode). Avoid cheap stamped sockets that develop intermittent contact after thermal cycling. For surface-mount designs, ensure the land pattern matches JEDEC PLCC68 with proper pad geometry - the leads extend slightly beyond the package body. Add a keep-out area under the socket for PLCC extraction tool access.
Address bus termination: at 16 MHz with address transitions in 25 ns, the address bus can exhibit significant ringing when driving multiple DRAM/ROM chips. Add 33 ohm series resistors near the CPU address pins if your design has long address traces (>50 mm) or many loads (>5 devices). The data bus benefits from similar treatment if multiple peripherals are mounted. Refer to the Motorola AN-E000 series application note for M68K bus termination guidance.
コンプライアンス情報
Part status Obsolete per NXP. RoHS, REACH, lead-free, and halogen-free status not confirmed in the provided data - request documentation from authorized distributors or NXP for engineering qualification. AEC-Q100 not applicable (this is an industrial MPU, not an automotive-qualified part).
