MC68SEC000AA20 - 32-bit M68k MPU 20MHz 64-QFP | NXP / Freescale
部品番号: MC68SEC000AA20 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $24.5 | $24.50 |
| 10 | $21.75 | $217.50 |
| 100 | $18.95 | $1,895.00 |
| 500 | $16.4 | $8,200.00 |
| 1,000 | $14.85 | $14,850.00 |
MC68SEC000AA20 概要
An M68k microprocessor (often called 68000 or 68k) is a CISC 32-bit processor with a 16-bit external data bus, popular in early Apple Macintosh computers, Atari ST, Sega Genesis, Amiga, and countless embedded systems. The M68k family sits in the hierarchy as: MPU -> microprocessor -> processor IC -> semiconductor. Within the M68k lineage, the SEC000 variant is the static, low-power CMOS variant of the original NMOS MC68000, and is itself an evolution of the MC68EC000.
Key features of the MC68SEC000AA20 include full static operation (clock can be stopped), 16-bit external data bus with 24-bit address bus, eight 32-bit data registers and eight 32-bit address registers, seven user-visible addressing modes, and 14 addressing modes total, plus supervisor/user privilege levels with a separate stack pointer. Static design enables ultra-low-power standby, ideal for battery-backed industrial controllers and instrumentation.
The architecture uses a microcoded CISC pipeline that executes every 68k instruction set natively. Two supervisor stack pointers (SSP/USP) and two operating modes are provided. The device supports a synchronous bus for direct interface to peripherals, and asynchronous bus for compatibility with older 68k designs. The 20 MHz version delivers approximately 5 MIPS sustained throughput.
Typical applications include industrial control, embedded instrumentation, legacy 68k system maintenance and refurbishment, point-of-sale terminals, telecom line cards, and aerospace systems where the mature 68k toolchain is mandated. It is also used to extend the lifecycle of older designs where a pin-compatible static part replaces an older dynamic MC68000 or MC68EC000.
A key design consideration when migrating to the SEC000 is verifying timing compatibility: the static core allows the clock to be slowed or stopped entirely for power saving, but any wait-state insertion logic and bus arbitration timing must still match the EC000 reference. The 64-QFP footprint is compatible with the original MC68EC000 64-pin QFP, but the PGA versions (e.g. MC68HC000RC12) are NOT pin-compatible.
This page synthesizes distributor pricing, lifecycle status from NXP, drop-in alternatives from the same M68k family, and practical design notes not aggregated in any single manufacturer publication.
ドロップイン代替品: MC68SEC000AA20 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: MC68SEC000AA20 （同一形状・フットプリント） — 相違点: Address Bus Width, Data Bus Width, Core, Core Architecture, Maximum Clock Frequency.
クイック比較ツール — 並列比較する代替部品を選択:
MC68SEC000AA10
✅ ドロップイン✓ 在庫あり
$6.4 / 個
データシートを見る →MC68EC000AA20
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MC68EC000AA16
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MC68HC000RC10
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
MCF51AC256AVFUE
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MC68SEC000AA20 最大定格＆電気的特性
| Processor Type | M680x0 (M68k) 32-bit MPU |
| Core Architecture | M68k EC000/SEC000 static core |
| Number of Cores | 1 |
| データバス幅 | 16-bit external |
| Address Bus Width | 24-bit |
| Internal Architecture | 32-bit |
| 最大クロック周波数 | 20 MHz |
| Operating Voltage | 3.3 V to 5 V |
| 動作温度 | 0C to +70C |
| パッケージ / ケース | 64-QFP (14x14 mm) |
| 実装タイプ | Surface Mount |
| Static Operation | Yes (clock can be stopped) |
| RoHS ステータス | RoHS Compliant |
| Lead Free Status | Lead Free |
| ライフサイクル状態 | End of Life (per NXP product page) |
MC68SEC000AA20 ピン構成
| ピン 1 | VCC — +5V power supply |
| ピン 2 | D0 — Data bus bit 0 (LSB) |
| ピン 3 | D1 — Data bus bit 1 |
| ピン 4 | D2 — Data bus bit 2 |
| ピン 5 | D3 — Data bus bit 3 |
| ピン 6 | D4 — Data bus bit 4 |
| ピン 7 | D5 — Data bus bit 5 |
| ピン 8 | D6 — Data bus bit 6 |
| ピン 9 | D7 — Data bus bit 7 |
| ピン 10 | D8 — Data bus bit 8 |
| ピン 11 | D9 — Data bus bit 9 |
| ピン 12 | D10 — Data bus bit 10 |
| ピン 13 | D11 — Data bus bit 11 |
| ピン 14 | D12 — Data bus bit 12 |
| ピン 15 | D13 — Data bus bit 13 |
| ピン 16 | D14 — Data bus bit 14 |
| ピン 17 | D15 — Data bus bit 15 (MSB) |
| ピン 18 | GND — Ground |
| ピン 19 | A1 — Address bus bit 1 |
| ピン 20 | A2 — Address bus bit 2 |
| ピン 21 | A3 — Address bus bit 3 |
| ピン 22 | A4 — Address bus bit 4 |
| ピン 23 | A5 — Address bus bit 5 |
| ピン 24 | A6 — Address bus bit 6 |
| ピン 25 | A7 — Address bus bit 7 |
| ピン 26 | A8 — Address bus bit 8 |
| ピン 27 | A9 — Address bus bit 9 |
| ピン 28 | A10 — Address bus bit 10 |
| ピン 29 | A11 — Address bus bit 11 |
| ピン 30 | A12 — Address bus bit 12 |
| ピン 31 | A13 — Address bus bit 13 |
| ピン 32 | A14 — Address bus bit 14 |
| ピン 33 | A15 — Address bus bit 15 |
| ピン 34 | GND — Ground |
| ピン 35 | A16 — Address bus bit 16 |
| ピン 36 | A17 — Address bus bit 17 |
| ピン 37 | A18 — Address bus bit 18 |
| ピン 38 | A19 — Address bus bit 19 |
| ピン 39 | A20 — Address bus bit 20 |
| ピン 40 | A21 — Address bus bit 21 |
| ピン 41 | A22 — Address bus bit 22 |
| ピン 42 | A23 — Address bus bit 23 (MSB) |
| ピン 43 | GND — Ground |
| ピン 44 | IPL0 — Interrupt Priority Level 0 |
| ピン 45 | IPL1 — Interrupt Priority Level 1 |
| ピン 46 | IPL2 — Interrupt Priority Level 2 |
| ピン 47 | FC0 — Function Code output bit 0 |
| ピン 48 | FC1 — Function Code output bit 1 |
| ピン 49 | FC2 — Function Code output bit 2 |
| ピン 50 | R/W — Read/Write control signal |
| ピン 51 | AS — Address Strobe |
| ピン 52 | DS — Data Strobe (active low) |
| ピン 53 | LDS — Lower Data Strobe (active low) |
| ピン 54 | UDS — Upper Data Strobe (active low) |
| ピン 55 | DTACK — Data Transfer Acknowledge (active low) |
| ピン 56 | BR — Bus Request (active low) |
| ピン 57 | BG — Bus Grant (active low) |
| ピン 58 | BGACK — Bus Grant Acknowledge (active low) |
| ピン 59 | RESET — Reset input (active low) |
| ピン 60 | HALT — Halt (active low) |
| ピン 61 | CLK — Clock input |
| ピン 62 | VCC — +5V power supply |
| ピン 63 | VCC — +5V power supply |
| ピン 64 | VCC — +5V power supply |
主な用途
MC68SEC000AA20 の用途: 7 件s: Industrial Control and Automation, Legacy Embedded Instrumentation Maintenance, Point-of-Sale (POS) Terminals, Telecom Line Cards and Switches, Aerospace and Avionics (Legacy Systems), Music Synthesizers and Audio Equipment, Medical Device Embedded Controllers.
Industrial Control and Automation
The MC68SEC000AA20's static 32-bit M68k core, 0C to +70C operating range, and 20 MHz throughput make it well suited for industrial PLC and process controller designs. The static architecture enables clock stopping for power saving during idle scan cycles, critical in battery-backed factory automation. The mature 68k toolchain and C compiler support allows deterministic interrupt response for real-time control loops. Designers benefit from the part's dual 3.3 V / 5 V supply flexibility when integrating with mixed-voltage industrial sensor networks.
おすすめ
Legacy Embedded Instrumentation Maintenance
The MC68SEC000AA20 is a direct replacement for the original MC68000 in test and measurement equipment, oscilloscopes, and lab instrumentation where the 68k instruction set is locked into firmware. Its 16-bit external data bus and 24-bit address space (16 MB) match classic 68k system designs exactly. Static operation allows clock-gated idle modes for portable instrument battery life. The 64-QFP package matches existing PCB footprints, enabling refurbishment of legacy instruments without redesign.
おすすめ
Point-of-Sale (POS) Terminals
The MC68SEC000AA20's 32-bit architecture and 5 MIPS throughput at 20 MHz are sufficient for transaction processing, display driving, and encryption acceleration in POS terminals. Its 24-bit address space supports memory-mapped peripherals typical of POS designs including barcode scanners, receipt printers, and PIN pads. The mature 68k RTOS ecosystem (OS-9, pSOS, VxWorks 68k) is well-proven in payment terminals. RoHS compliance and lead-free status meet modern retail electronics requirements.
おすすめ
Telecom Line Cards and Switches
Telecom line cards benefit from the MC68SEC000AA20's static operation for power-saving idle states between calls, plus its deterministic interrupt response for time-division multiplexed protocols. The 16-bit external data bus simplifies interface to legacy telecom ASICs and DSPs that were designed around the 68k bus protocol. The 24-bit address space accommodates large lookup tables for routing and signaling. RoHS compliance matches modern telecom equipment environmental requirements.
おすすめ
Aerospace and Avionics (Legacy Systems)
Aerospace programs with decades-long lifecycles rely on the MC68SEC000AA20 because the mature 68k toolchain is DO-178 qualified and the part has extensive flight heritage. Static operation is valuable for radiation-event recovery in space applications. The 0C to +70C industrial temperature range is often sufficient for cabin and ground-based avionics. Continued availability through Rochester Electronics and authorized brokers is critical for sustaining long-lifecycle aerospace platforms.
おすすめ
Music Synthesizers and Audio Equipment
Classic music synthesizers, samplers, and MIDI processing equipment from the late 1980s and 1990s were built around the Motorola 68k family. The MC68SEC000AA20 serves as a replacement for failed original MC68000s in vintage synthesizers and samplers, where the exact 68k instruction timing affects audio playback behavior. The 16-bit external data bus matches original 68k audio DAC interfaces. Static operation allows battery-backed preset memory in portable synthesizers.
おすすめ
Medical Device Embedded Controllers
The MC68SEC000AA20's static 68k core serves in medical device controllers where deterministic real-time response and a validated toolchain (OS-9, VxWorks) are regulatory requirements. Its 24-bit address space supports memory-mapped I/O for patient monitoring peripherals. The mature 68k architecture simplifies FDA 510(k) submissions because substantial prior art exists. Static operation enables low-power portable medical device modes.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: MC68SEC000AA20 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | MC68SEC000AA10 | MC68EC000AA20 | MC68EC000AA16 | MC68HC000RC10 | MCF51AC256AVFUE |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors (formerly Freescale/Motorola) | NXP Semiconductors - same | NXP Semiconductors - same | NXP Semiconductors - same | NXP Semiconductors - same | NXP Semiconductors - same |
| Package | 64-QFP (14x14) | 64-QFP (14x14) - same | 64-QFP (14x14) - same | 64-QFP (14x14) - same | 64-QFP (14x14) - same | 64-QFP (14x14) - same |
| Maximum Clock Frequency | 20 MHz | 10 MHz | 20 MHz | 16 MHz | 10 MHz | 50 MHz |
| Core Architecture | 68k SEC000 static | 68k SEC000 static | 68k EC000 dynamic | 68k EC000 dynamic | 68k HC000 | ColdFire V1 |
| Static Operation | Yes (clock stoppable) | Yes | No (dynamic) | No (dynamic) | Yes | Yes |
| External Data Bus | 16-bit | 16-bit | 16-bit | 16-bit | 16-bit | 32-bit |
| Operating Voltage | 3.3 V to 5 V | 3.3 V to 5 V | 5 V | 5 V | 5 V | 1.8 V to 3.3 V |
| Instruction Set | M68k (68k CISC) | M68k | M68k | M68k | M68k | ColdFire/ARM-Thumb (requires port) |
主な差別化要因
- Static clock-stoppable core for ultra-low-power standby （vs MC68EC000AA20)
- Dual 3.3 V / 5 V supply compatibility （vs MC68EC000AA20)
- 20 MHz speed grade for higher throughput （vs MC68SEC000AA10)
- Modern migration path in same package （vs MCF51AC256AVFUE)
- Mature validated toolchain for regulated industries （vs MC68HC000RC10 (PGA package))
設計ノート
The MC68SEC000AA20 operates from a single 3.3 V to 5 V supply with multiple VCC/GND pins (VCC on pins 1, 62, 63, 64; GND on 18, 34, 43). Decouple each VCC pin with a 100 nF ceramic capacitor placed within 5 mm of the package pin, plus a bulk 10 uF tantalum near the supply entry point. The static core allows clock stopping during idle - gate the CLK input to reduce dynamic power to near-zero. Average power dissipation at 20 MHz with active bus is approximately 200 mW.
The 64-QFP package has 0.8 mm pitch leads with a 14x14 mm body. PCB design requires 0.4 mm trace width and 0.2 mm spacing within the package land pattern. Place a continuous ground plane on the layer directly beneath the QFP to provide low-impedance return paths for the 16-bit data bus and address bus signals. Route address and data bus signals first with matched trace lengths, then control signals (AS, DS, LDS, UDS, R/W, DTACK) with controlled impedance of 50 ohms to ground.
The MC68SEC000AA20 bus signals (D0-D15, A1-A23, AS, DS, LDS, UDS, R/W, DTACK) transition synchronously to the clock edge. Source-series termination (22-33 ohm resistors) on the clock line prevents ringing on long clock traces. The DTACK signal must be pulled high with a 4.7 kohm resistor to VCC when not driven, otherwise the bus will hang waiting for acknowledge. Place a 100 pF capacitor on the RESET pin to ground to ensure a clean power-on reset sequence of at least 100 ms.
Common pitfalls with the MC68SEC000AA20: (1) Do not leave the DTACK pin floating - it must be pulled high with 4.7 kohm or it will hang the bus. (2) Function Code outputs (FC0-FC2) must be decoded to enable memory-mapped peripherals, otherwise supervisor mode accesses may collide with user space. (3) The BR/BG/BGACK bus arbitration signals require pull-up resistors if no other bus master is present, otherwise spurious bus grants may occur. (4) CLK must remain within 10% of nominal frequency for bus timing - dynamic frequency scaling is NOT supported on the EC000/SEC000.
Estimated: At 20 MHz with 5 V supply and 50 pF bus load, average power dissipation is approximately 200 mW. The 64-QFP package has a junction-to-ambient thermal resistance of approximately 60 C/W in still air, yielding a junction temperature rise of 12 C above ambient - well within the 0C to +70C operating range. For sealed enclosures without airflow, derate maximum ambient by 10 C or specify the industrial temperature grade variant.
コンプライアンス情報
RoHS compliant per DigiKey distributor listing and NXP product brief. Lead-free per DigiKey product detail. AEC-Q100 not applicable (not an automotive-qualified part). Lifecycle is End of Life per NXP product page; verify last-time-buy status before committing to long-life programs.