MCIMX6D6AVT08AC - i.MX 6Dual 852MHz ARM Cortex-A9 MPU | NXP
部品番号: MCIMX6D6AVT08AC ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $86.5 | $86.50 |
| 10 | $78.4 | $784.00 |
| 100 | $71.2 | $7,120.00 |
| 500 | $64.85 | $32,425.00 |
| 1,000 | $58.1 | $58,100.00 |
MCIMX6D6AVT08AC 概要
What is a MPU? A microprocessor unit (MPU) is a System-on-Chip (SoC) computing platform that integrates one or more application CPU cores together with on-chip peripherals, graphics, and memory controllers on a single die. The i.MX 6Dual sits within the MPU > applications processor > multimedia SoC hierarchy and is targeted at operating systems (Linux, Android, Windows Embedded) running complex graphical user interfaces, video playback, and connected peripherals.
Key features of this variant include 852 MHz maximum ARM Cortex-A9 core frequency, 32 KB L1 instruction cache and 32 KB L1 data cache per core, 1 MB unified L2 cache shared across both cores, integrated 2D and 3D graphics engines (Vivante GC2000 plus GC355 GC320), dual HDMI/LVDS display interfaces with 1080p60 encode/decode, dual USB 2.0 with PHY, Gigabit Ethernet MAC, MLB and PCIe support, and hardware cryptographic accelerators for AES, SHA, and RNG. The integrated Smart Speed technology enables per-core DVFS to extend idle runtime in battery-powered panels.
The device architecture is built on a 40 nm low-power CMOS process, enabling the entire SoC to operate in extended-temperature industrial environments. The 624-pin FCBGA with 0.8 mm ball pitch supports a high-pin-count integration of multiple display, memory, and connectivity interfaces while keeping the PCB footprint compact at 21 mm x 21 mm. The variant designation -VT08A indicates 852 MHz industrial-grade (extended) temperature range and DDR3/LPDDR2 memory interface compatibility.
Typical applications for this MPU include industrial HMI panels, automotive infotainment head units, point-of-sale terminals, patient monitors, and digital signage controllers. The combination of dual ARM cores and on-chip GPU enables smooth Qt/Web/HTML5 rendering without an external graphics chip. NXP recommends pairing the SoC with the PF3000 PMIC, SGTL5000 audio codec, and an eMMC 5.0+ NAND flash for typical reference designs.
When designing with this part, allocate PCB area for the 21 mm x 21 mm FCBGA land pattern with controlled-impedance routing for DDR3 traces and follow NXP's i.MX 6 layout guidelines (AN4156). Ensure a stable 1.8 V/2.8 V/3.3 V supply rail sequencing and adequate decoupling near each power domain to meet DDR jitter requirements.
This page synthesizes NXP specifications, distributor stock and pricing, real drop-in alternatives, and practical design notes not consolidated elsewhere.
ドロップイン代替品: MCIMX6D6AVT08AC — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
MCIMX6D6AVT08AD
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MCIMX6D6AVT08AE
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MCIMX6D6AVT08ACR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MCIMX6D6AVT08ADR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MCIMX6D4AVT08ACR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MCIMX6Q6AVT08AC
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
MCIMX6D6AVT08AC 最大定格＆電気的特性
| Core Architecture | ARM Cortex-A9 |
| Number of Cores | 2 (Dual) |
| Maximum CPU Frequency | 852 MHz |
| データバス幅 | 32-bit |
| L1 Instruction Cache | 32 KB per core |
| L1 Data Cache | 32 KB per core |
| L2 Cache | 1 MB unified |
| Graphics | 2D + 3D GPU (Vivante GC2000 + GC355 + GC320) |
| パッケージ | 624-FCBGA (21 mm x 21 mm, 0.8 mm pitch) |
| 実装タイプ | Surface Mount (BGA) |
| 動作温度 | -40C to +105C (Automotive Grade) |
| 電源電圧 | 1.8 V / 2.8 V / 3.3 V |
| Memory Interface | DDR3 / LPDDR2 / NAND / eMMC |
| Display Interfaces | HDMI, LVDS (dual), MIPI-DSI (optional) |
| USB | 2 x USB 2.0 with integrated PHY |
| Ethernet MAC | 10/100/1000 Mbps |
| RoHS ステータス | Compliant |
| Process Technology | 40 nm CMOS |
| NEON SIMD Engine | Yes |
| Cryptographic Accelerators | AES, SHA, RNG (CAAM) |
MCIMX6D6AVT08AC 624-fcbga (21 mm x 21 mm, 0.8 mm pitch) ピン配置ガイド
MCIMX6D6AVT08AC (624-fcbga (21 mm x 21 mm, 0.8 mm pitch) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: MCIMX6D6AVT08AC.
詳細は データシート をご参照ください。
主な用途
MCIMX6D6AVT08AC の用途: 6 件s: Industrial HMI Panels, Automotive Infotainment Head Units, Point-of-Sale Terminals, Patient Monitoring and Medical Imaging, Digital Signage and Kiosks, Industrial Printers and Imaging.
Industrial HMI Panels
Why this MPN fits this application: The MCIMX6D6AVT08AC's dual ARM Cortex-A9 cores at 852 MHz combined with integrated Vivante 2D/3D GPU deliver sufficient throughput for Qt/Web-based industrial human-machine interface panels running real-time control visualizations. The 1 MB unified L2 cache plus integrated display controllers drive 1080p60 graphical outputs without external graphics silicon. Performance and circuit role: Placed on a six-layer PCB with DDR3 memory, the SoC handles multi-threaded fieldbus communication (EtherCAT, PROFINET) in parallel with 2D/3D HMI rendering. The -40C to +105C temperature range supports enclosure-mounted industrial cabinets and roadside panel deployments. Power supply uses the NXP PF3000 PMIC for 1.8 V/2.8 V/3.3 V sequencing.
おすすめ
Automotive Infotainment Head Units
Why this MPN fits this application: The automotive-grade -40C to +105C operating range plus dual ARM Cortex-A9 cores running at 852 MHz make the MCIMX6D6AVT08AC suitable for in-vehicle infotainment head units that render navigation, audio, and rear-seat entertainment. NEON SIMD accelerates H.264/AVC and VP8 video streams. Performance and circuit role: The SoC drives HDMI plus dual LVDS display outputs to a center stack display and instrument cluster. Hardware AES plus SHA accelerators (CAAM) handle secure boot and OEM content protection. Off-chip DDR3 is required for video frame buffers; eMMC 5.0 stores the OS image. AEC-Q100 module-level qualification is the integrator's responsibility.
おすすめ
Point-of-Sale Terminals
Why this MPN fits this application: The MCIMX6D6AVT08AC's hardware cryptographic accelerator plus on-chip Ethernet MAC and dual USB 2.0 with PHY suit POS terminals that demand PCI-PTS grade security and reliable peripheral networking. Dual Cortex-A9 cores run payment-grade Linux in parallel with EMV/chip card state machines. Performance and circuit role: Combined with tamper-detection inputs routed to GPIOs, the SoC secures PIN entry and transaction signing. Integrated GPU drives the LCD touch display, while the Ethernet MAC connects the terminal to a payment processor over WAN or LAN. The 624-FCBGA's compact 21 mm footprint suits slimline card-reader enclosures.
おすすめ
Patient Monitoring and Medical Imaging
Why this MPN fits this application: The MCIMX6D6AVT08AC delivers low-latency signal processing and rich graphical rendering required for patient monitors visualizing SpO2, ECG, and capnography waveforms. The two Cortex-A9 cores plus Vivante GPU drive a high-resolution WVGA or 1080p TFT LCD without an external graphics chip. Performance and circuit role: Placed on a board with isolated AFE front-end, the SoC performs real-time DSP on ECG samples while simultaneously rendering waveforms. Hardware cryptographic engine secures DICOM data at rest. The FCBGA's 0.8 mm pitch allows miniaturization in handheld patient monitor form factors.
おすすめ
Digital Signage and Kiosks
Why this MPN fits this application: This MPN's dual core 852 MHz ARM Cortex-A9 with on-chip 2D/3D GPU drives full HD digital signage and interactive kiosk displays at low BOM cost. HDMI output supports commercial display panels, while Gigabit Ethernet handles network content updates and remote diagnostics. Performance and circuit role: The SoC renders HTML5-based interactive content, dual LVDS outputs support a primary plus secondary customer-facing display. Hardware video decode handles H.264 1080p streams from a media server. The 21 mm FCBGA footprint allows slimline chassis designs for floor-standing kiosks.
おすすめ
Industrial Printers and Imaging
Why this MPN fits this application: NXP i.MX 6Dual silicon integrates hardware video engines that decode print job previews plus the dual Cortex-A9 cores that process rendering tasks in parallel. The MCIMX6D6AVT08AC's Ethernet MAC and dual USB 2.0 PHYs handle print-server communication and operator panel connectivity. Performance and circuit role: The SoC is paired with external DDR3 for print raster buffers and an eMMC for firmware. The hardware accelerators compress and decompress print jobs without CPU intervention, freeing the Cortex-A9 for protocol handling (PCL, PostScript, PDF). Industrial temperature range allows installation in factory print rooms.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: MCIMX6D6AVT08AC — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | MCIMX6D6AVT08AD | MCIMX6D6AVT08AE | MCIMX6D6AVT08ACR | MCIMX6D6AVT08ADR | MCIMX6D4AVT08ACR | MCIMX6Q6AVT08AC |
|---|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 624-FCBGA (21x21) | 624-FCBGA (21x21) - same | 624-FCBGA (21x21) - same | 624-FCBGA (21x21) - same | 624-FCBGA (21x21) - same | 624-FCBGA (21x21) - same | 624-FCBGA (21x21) - same |
| Core Architecture | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 (DualLite variant) | Quad ARM Cortex-A9 |
| Maximum CPU Frequency | 852 MHz | 852 MHz | 852 MHz | 852 MHz | 852 MHz | 852 MHz | 852 MHz |
| Number of Cores | 2 | 2 | 2 | 2 | 2 | 2 (DualLite) | 4 |
| Operating Temperature | -40C to +105C | -40C to +105C | -40C to +105C | -40C to +105C | -40C to +105C | -40C to +105C | -40C to +105C |
| Silicon Revision | AC (original) | AD (updated) | AE (latest) | AC (original, R packing) | AD (updated, R packing) | AC variant of DualLite | AC variant of Quad |
| Lifecycle Status | NRND | Active (recommended replacement) | Active | NRND | Active | NRND | NRND |
主な差別化要因
- Updated silicon revision with bug-fix history （vs MCIMX6D6AVT08AD)
- Greater CPU parallelism for multi-threaded workloads （vs MCIMX6D6AVT08ACR vs MCIMX6Q6AVT08AC)
- Different memory/feature tier within the same package （vs MCIMX6D4AVT08ACR)
設計ノート
Estimated: At full SoC load (Dual Cortex-A9 @ 852 MHz, 3D GPU, DDR3 traffic), the FCBGA package junction-to-ambient thermal resistance of approximately 13 C/W on a 6-layer test PCB implies a T_j rise of about 24 W / 13 C/W, which is unrealistic. Real Tj is governed by power consumption of roughly 2-3 W typical, giving a 30-40 C rise over ambient at 1.5 m/s airflow. A thermal interface material (TIM) plus spreader plate is mandatory for closed enclosures; derate performance above +85 C ambient.
Per NXP AN4156 Hardware Design Guide, use a minimum 6-layer stack-up with microvia-in-pad for the 0.8 mm BGA escape. Pair the SoC with a PF3000 PMIC and route DDR3 with 50 ohm single-ended controlled impedance; keep trace lengths matched within 25 mils for byte groups and 100 mils for byte-to-byte to meet DDR3 1066 Mbps specification.
Use the PF3000 PMIC for correct power-up sequencing: 1.8 V core must lead, then 2.8 V analog and 3.3 V I/O. Add bulk decoupling capacitors (22 uF + 0.1 uF X7R) within 5 mm of the SoC's power balls. NVCC_x I/O groups each need their own decoupling region. Failure to follow sequencing can cause boot failures or unrecoverable latch-up.
Do not assume the i.MX 6Dual pinout is identical to the i.MX 6Quad; while the 624-FCBGA ball-map is shared at the Freescale-NXP legacy level for the i.MX 6 family, double-check the reference manual before board respins. Also avoid leaving boot configuration pins floating; strap them correctly per the system boot chapter or the device will not boot from the desired source (NAND vs SD vs eMMC).
コンプライアンス情報
RoHS compliant per NXP product page; AEC-Q100 is board-level integrator responsibility for this i.MX 6Dual automotive part.
