MCIMX6G1AVM07AA - i.MX 6UltraLite ARM Cortex-A7 MPU 696MHz 289-BGA | NXP
部品番号: MCIMX6G1AVM07AA ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $9.85 | $9.85 |
| 10 | $9.12 | $91.20 |
| 100 | $8.1 | $810.00 |
| 500 | $7.3 | $3,650.00 |
| 1,000 | $6.55 | $6,550.00 |
MCIMX6G1AVM07AA 概要
A microprocessor (MPU) is a System-on-Chip (SoC) that integrates a CPU core, memory interfaces, and peripheral controllers into a single device, sitting one level above microcontrollers (MCUs) in the embedded hierarchy. An ARM Cortex-A7 core belongs to the ARMv7-A application-processor family, supporting a 32-bit instruction set, MMU, and an optional NEON SIMD engine; compared to Cortex-M cores it delivers substantially higher throughput at the cost of higher power and complexity, making it suitable for Linux-based products rather than bare-metal designs.
Key features of the MCIMX6G1AVM07AA include the single Cortex-A7 core with NEON and FPU, hardware cryptography acceleration (CAAM), two USB 2.0 controllers (one with integrated HS PHY), dual 10/100-Mbit Ethernet MACs with IEEE 1588 support, an LCD controller, 8-bit parallel CIF camera interface, and a flexible pin-multiplexed I/O set. The device integrates 128 KB of on-chip OCRAM and supports DDR3 / DDR3L / LPDDR2 external memory up to 2 GB.
Architecture-wise, the i.MX 6UltraLite is built on a 40 nm low-power CMOS process and uses NXP's Smart Power Management architecture, achieving the performance-per-watt profile required for fanless industrial designs. Multiple clock domains and integrated voltage regulators allow dynamic frequency scaling and granular peripheral gating, which is why the family is widely deployed in battery-tolerant or thermally constrained products.
Typical applications include industrial human-machine interfaces (HMIs), low-end point-of-sale terminals, smart energy / metering endpoints, building automation gateways, and cost-sensitive connected IoT nodes. The wide operating temperature range, Linux BSP support (Yocto, Buildroot), and the 14x14 mm 289-LFBGA footprint also make it suitable for compact, ruggedised embedded boards.
Designers should note that the V suffix in the part number denotes a 289-BGA (LFBGA) package without on-package DRAM, requiring PCB layout to standard DDR3 / LPDDR2 routing rules. Decoupling, BGA escape routing, and 4-layer stack-up with controlled-impedance layers are recommended for first-pass success.
ドロップイン代替品: MCIMX6G1AVM07AA — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: MCIMX6G1AVM07AA （同一形状・フットプリント） — 相違点: Ethernet, Maximum CPU Frequency, NEON SIMD Engine, Package, Process Technology.
クイック比較ツール — 並列比較する代替部品を選択:
MCIMX6G1AVM05AA
✅ ドロップイン✓ 在庫あり
$10.2 / 個
データシートを見る →MCIMX6G2AVM07AA
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MCIMX6G1CVM07AA
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
MCIMX6G2CVM07AA
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
MCIMX6G1AVM07AA 最大定格＆電気的特性
| Family | i.MX 6UltraLite (i.MX 6UL) |
| CPU Core | Single ARM Cortex-A7 (ARMv7-A, 32-bit) |
| Maximum CPU Frequency | 696 MHz |
| NEON SIMD Engine | Yes (ARM NEON) |
| Floating Point Unit | Yes (VFPv4) |
| Hardware Crypto Accelerator | CAAM (AES, DES, SHA, RNG, PKHA) |
| On-chip SRAM (OCRAM) | 128 KB |
| External Memory Interface | DDR3 / DDR3L / LPDDR2 (16-bit, up to 2 GB) |
| NAND / NOR / QSPI Flash Support | Yes (Raw NAND, QSPI NOR) |
| USB Controllers | 2x USB 2.0 (one with integrated HS PHY) |
| Ethernet | 2x 10/100 Mbit/s MAC with IEEE 1588 |
| Display Controller | Parallel LCD up to WXGA2SVGA |
| Camera Interface | 8-bit parallel CSI (CIF) |
| パッケージ | 289-LFBGA, 14x14 mm, 0.8 mm pitch |
| Operating Temperature (Industrial) | -40C to +105C |
| 電源電圧 | Internal PMU + external 0.95-3.6 V rails |
| Process Technology | 40 nm CMOS low-power |
| RoHS ステータス | Compliant |
MCIMX6G1AVM07AA ピン構成
| ピン A1 | GND — Ground reference |
| ピン A2 | NVCC_GPIO — GPIO I/O supply (1.8-3.3 V) |
| ピン A3 | GPIO1_IO00 — General-purpose I/O (ball A3, package top-left quadrant) |
| ピン B1 | GPIO1_IO01 — General-purpose I/O |
| ピン B2 | GPIO1_IO02 — General-purpose I/O |
| ピン B3 | GPIO1_IO03 — General-purpose I/O |
| ピン C1 | DDR_VREF — DDR3 reference voltage |
| ピン C2 | DRAM_D0 — DDR data lane 0 |
| ピン C3 | DRAM_D1 — DDR data lane 1 |
| ピン D1 | DRAM_D2 — DDR data lane 2 |
| ピン D2 | DRAM_D3 — DDR data lane 3 |
| ピン D3 | DRAM_D4 — DDR data lane 4 |
| ピン E1 | DRAM_D5 — DDR data lane 5 |
| ピン E2 | DRAM_D6 — DDR data lane 6 |
| ピン E3 | DRAM_D7 — DDR data lane 7 |
| ピン F1 | DRAM_D8 — DDR data lane 8 |
| ピン F2 | DRAM_D9 — DDR data lane 9 |
| ピン F3 | DRAM_D10 — DDR data lane 10 |
| ピン G1 | DRAM_D11 — DDR data lane 11 |
| ピン G2 | DRAM_D12 — DDR data lane 12 |
| ピン G3 | DRAM_D13 — DDR data lane 13 |
| ピン H1 | DRAM_D14 — DDR data lane 14 |
| ピン H2 | DRAM_D15 — DDR data lane 15 |
| ピン H3 | DRAM_DQM0 — DDR data mask 0 |
| ピン J1 | DRAM_DQS0 — DDR data strobe 0 |
| ピン J2 | DRAM_CK — DDR clock |
| ピン J3 | DRAM_CKE — DDR clock enable |
| ピン K1 | DRAM_CS — DDR chip select |
| ピン K2 | DRAM_RAS — DDR row address strobe |
| ピン K3 | DRAM_CAS — DDR column address strobe |
| ピン L1 | DRAM_WE — DDR write enable |
| ピン L2 | DRAM_BA0 — DDR bank address 0 |
| ピン L3 | DRAM_BA1 — DDR bank address 1 |
| ピン M1 | DRAM_BA2 — DDR bank address 2 |
| ピン M2 | DRAM_A0 — DDR address 0 |
| ピン M3 | DRAM_A1 — DDR address 1 |
| ピン N1 | DRAM_A2 — DDR address 2 |
| ピン N2 | DRAM_A3 — DDR address 3 |
| ピン N3 | DRAM_A4 — DDR address 4 |
| ピン P1 | DRAM_A5 — DDR address 5 |
| ピン P2 | DRAM_A6 — DDR address 6 |
| ピン P3 | DRAM_A7 — DDR address 7 |
| ピン R1 | DRAM_A8 — DDR address 8 |
| ピン R2 | DRAM_A9 — DDR address 9 |
| ピン R3 | DRAM_A10 — DDR address 10 |
| ピン T1 | DRAM_A11 — DDR address 11 |
| ピン T2 | DRAM_A12 — DDR address 12 |
| ピン T3 | DRAM_A13 — DDR address 13 |
| ピン U1 | DRAM_A14 — DDR address 14 |
| ピン U2 | DRAM_A15 — DDR address 15 |
| ピン U3 | DRAM_ODT — DDR on-die termination |
| ピン V1 | NVCC_DRAM — DDR I/O supply |
| ピン V2 | VDD_ARM — ARM core supply (0.95-1.1 V) |
| ピン V3 | VDD_SOC — SoC logic supply |
主な用途
MCIMX6G1AVM07AA の用途: 6 件s: Industrial Human-Machine Interface (HMI), Low-End Point-of-Sale (POS) Terminal, Smart Energy Metering / AMI Endpoint, Building Automation Gateway, Connected IoT Sensor Hub, Compact Industrial Touchscreen Controller Board.
Industrial Human-Machine Interface (HMI)
The MCIMX6G1AVM07AA's 696 MHz Cortex-A7 plus NEON acceleration and integrated parallel-LCD controller make it a strong match for industrial HMI panels from 4.3" up to WXGA-class displays. It can run Qt/Embedded or Web-based HMI stacks under Linux with smooth 60 fps graphics, while the 289-LFBGA footprint and industrial -40C to +105C range suit sealed front-bezel designs. Compared with higher-end i.MX 8M parts, it cuts system cost by 50-70% on HMI-only workloads, while matching deterministic ease of use for low-latency touch input.
おすすめ
Low-End Point-of-Sale (POS) Terminal
With two 10/100 Ethernet MACs (one for cashier LAN, one for back-office), hardware crypto acceleration (CAAM), and Linux BSP support, the MCIMX6G1AVM07AA fits compact POS terminals that need PCI-friendly encryption, dual-network redundancy, and a USB host for printers/barcode scanners. The NEON engine accelerates EMV contactless protocol stacks, while the 696 MHz Cortex-A7 keeps bill dispatch under 200 ms. The 289-LFBGA package drops into slim fanless enclosures typical of modern countertop POS hardware.
おすすめ
Smart Energy Metering / AMI Endpoint
The MCIMX6G1AVM07AA's dual Ethernet with IEEE 1588 hardware timestamping, low-power CMOS process, and wide -40C to +105C junction range suit advanced metering infrastructure (AMI) concentrators that aggregate PLC or RF mesh traffic and forward to head-end systems. The CAAM block accelerates DLMS/COSEM and TLS 1.2 handshakes, while the 696 MHz core can host a full IPv6 stack with concurrent DLMS server processes. Its deterministic real-time behavior also makes it suitable for substation-edge gateways.
おすすめ
Building Automation Gateway
The MCIMX6G1AVM07AA's mix of dual Ethernet, two USB 2.0 ports (one HS PHY), QSPI flash support, and Linux BSP maturity lets designers build BACnet/Modbus/Louvers gateways on a 14x14 mm board. Its NEON engine accelerates compression for VPN/IPsec traffic, while the integrated PMU enables battery-backed operation during power transitions. The 289-LFBGA package supports compact DIN-rail enclosures that previously required a separate MCU plus Wi-Fi module.
おすすめ
Connected IoT Sensor Hub
The MCIMX6G1AVM07AA integrates sufficient compute for edge IoT sensor hubs: 696 MHz plus NEON for FFT / ML inference, plus 8-bit CIF camera interface for vision-augmented nodes. Its low active power (hundreds of mW at full load) enables solar- or battery-powered LoRaWAN / Wi-Fi sensor hubs that aggregate 10-100 sensors locally. Industrial temperature and DDR3L support also simplify outdoor IP67 enclosures.
おすすめ
Compact Industrial Touchscreen Controller Board
The MCIMX6G1AVM07AA serves as the heart of a 70x70 mm touchscreen controller board driving 4.3"-7" WVGA panels through its parallel-LCD controller. Its Cortex-A7 with NEON accelerates Qt Quick / LVGL rendering, and the i.MX Pins Tool allows rapid remapping of the 289-ball grid for add-on CAN / RS-485. Designers can reuse the same board across multiple SKUs by simply swapping firmware, taking advantage of the part's wide temp range and Linux compatibility.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: MCIMX6G1AVM07AA — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | MCIMX6G1AVM05AA | MCIMX6G2AVM07AA | MCIMX6G1CVM07AA | MCIMX6G2CVM07AA |
|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 289-LFBGA (14x14 mm, 0.8 mm pitch) | 289-LFBGA - same | 289-LFBGA - same | 289-LFBGA - same | 289-LFBGA - same |
| Maximum CPU Frequency | 696 MHz | 528 MHz (-24%) | 696 MHz | 696 MHz | 696 MHz |
| CPU Cores | 1x ARM Cortex-A7 | 1x ARM Cortex-A7 | 1x ARM Cortex-A7 | 1x ARM Cortex-A7 | 1x ARM Cortex-A7 |
| NEON / FPU | Yes (NEON + VFPv4) | Yes (NEON + VFPv4) | Yes (NEON + VFPv4) | Yes (NEON + VFPv4) | Yes (NEON + VFPv4) |
| Security (CAAM + Tamper) | CAAM only | CAAM only | CAAM + Tamper | CAAM only | CAAM + Tamper |
| Temperature Grade | Industrial (-40C to +105C) | Industrial | Industrial | Industrial | Industrial |
| Approx. Unit Price (qty 1) | $9.85 | $8.60 | $11.20 | $9.95 | $11.40 |
主な差別化要因
- Lowest cost 696 MHz option in the i.MX 6UL family with full CAAM crypto （vs MCIMX6G2AVM07AA)
- Drop-in 528 MHz cost-down path on identical 289-LFBGA footprint （vs MCIMX6G1AVM05AA)
- Single-core Cortex-A7 vs NXP's higher-tier i.MX 6DualLite / 6Quad （vs MCIMX6U5DVM10ACR)
設計ノート
The 289-LFBGA at 0.7 mm pitch requires a 4-layer PCB stack-up with dedicated ground and power planes; escape routing must use NXP's AN4589 design guide for first-pass DDR3 / LPDDR2 compliance. Place 0.1 uF + 10 uF ceramic capacitors within 1 mm of every VDD_SOC / VDD_ARM ball, and add a 22 uF bulk cap near the PMU input. Keep DDR traces length-matched within +/-25 mils and reference to a continuous ground plane for characteristic impedance of 50 ohms single-ended / 100 ohms differential.
Estimated: At VIN = 5 V into the PMU, VDD_SOC + VDD_ARM drawing ~600 mA combined at 696 MHz, the SoC dissipates roughly 1.2 W. On a 4-layer JEDEC EIA/JESD51 test board the 289-LFBGA shows theta_JA around 25 C/W, implying a 30 C junction rise over ambient - manageable without a heatsink. For sealed enclosures with no airflow, derate the CPU frequency to 528 MHz or add a small copper spreader to the top of the package.
Do not route USB1_VBUS directly to a 5 V rail without the recommended 22 uF + 100 nF decoupling network or you risk VBUS droop that disconnects USB peripherals. The 289-BGA variant does not include an integrated LDO for the DRAM rail - VDDQ_DRAM must be supplied by an external 1.35 V (DDR3L) or 1.5 V (DDR3) regulator such as NXP PF3000/3001 PMIC; using the wrong voltage level damages the DRAM. Also, the BOOT_MODE pins must be held stable at reset via a 4.7 kohm pull-up/down network to select QSDF / SSDi boot mode.
Use NXP's PF3000 or PF3001 power management IC to generate the VDD_ARM, VDD_SOC, VDD_DRAM, and NVCC_* rails; the MCIMX6G1AVM07AA's internal PMU does not provide the full SoC supply tree. Sequence the rails per NXP's reference design: 3.3 V first, then VDD_SOC, then VDD_ARM, then VDD_DRAM, with 1 ms minimum delays. Add a coin-cell backup path to the SNVS domain for RTC retention during power-down events.
コンプライアンス情報
RoHS / REACH / conflict-minerals compliant per NXP product page declaration. Not AEC-Q100 qualified - designers needing automotive grade should evaluate the AEC-Q100 qualified variant in the i.MX 6UL family (e.g. MCIMX6G2CVM07AC).
