MCIMX6X3EVO10AB - i.MX 6SoloX ARM A9/M4 MPU | NXP
部品番号: MCIMX6X3EVO10AB ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $28.04 | $28.04 |
| 10 | $25.62 | $256.20 |
| 100 | $23.1 | $2,310.00 |
| 500 | $21.05 | $10,525.00 |
| 1,000 | $19.2 | $19,200.00 |
MCIMX6X3EVO10AB 概要
An applications processor (AP) is a system-on-chip (SoC) class integrated circuit designed to run a full operating system such as Linux, Android, or QNX, as opposed to a microcontroller which typically runs bare-metal or an RTOS. The i.MX 6SoloX sits in the i.MX 6 family hierarchy between the i.MX 6UltraLite (Cortex-A7 only, low power) and the i.MX 6Dual/6Quad (Cortex-A9 multicore) variants. The asymmetric A9 + M4 combination allows real-time deterministic tasks to be isolated from the application OS, a topology commonly used in industrial IoT gateways, telematics control units, and secure HMI panels where functional safety and responsiveness co-exist with rich graphics.
Key features of the MCIMX6X3EVO10AB include 32 KB I-cache and 32 KB D-cache on the Cortex-A9, NEON SIMD media engine, hardware accelerated 2D/3D graphics via the Vivante GC400T GPU, dual-port Display Controller and LCDIF supporting up to 1080p, dual CAN-FD, dual 10/100/1000 Gigabit Ethernet with AVB, two USB 2.0 controllers with PHYs, three SD/MMC ports, and PCIe 2.0. Hardware security is provided through ARM TrustZone, secure boot, and on-chip crypto accelerators (AES, SHA, DES).
Architecturally the SoC pairs the high-throughput A9 out-of-order pipeline for the application OS and graphical user interface with the deterministic M4 for hard-real-time I/O handling - a layout that lets a single chip replace what would otherwise be an MPU plus a separate MCU. The part supports -40C to +105C Tj operation, suiting industrial and automotive cabinet environments, and uses NXP's 40 nm low-power process.
Typical applications include automotive infotainment head units, industrial HMI panels with touch + secure boot, telematics control units, smart energy gateways, and connected home control hubs requiring real-time fieldbus + a Linux application layer. Drop-in same-package variants such as the MCIMX6X3EVN10AB (industrial temp grade variant within the same die family) and MCIMX6X2EVN10AB (related 6DualLite-class in the same 400-MAPBGA) allow board reuse when the temperature grade or core count changes.
When designing with this device, ensure the PCB follows NXP's hardware design guide for the 17 mm x 17 mm MAPBGA, including microvia stack-up, length-matched DDR3 routing, and a reference clock distribution that meets the jitter mask for ENET. Software bring-up requires selecting the correct boot configuration (eFuses vs SD card) and validating TrustZone partition between A9 and M4 address spaces.
This page synthesises authorised distributor pricing, same-package drop-in alternatives in the same NXP i.MX 6 series, and practical bring-up notes not found in the standalone datasheet PDF.
ドロップイン代替品: MCIMX6X3EVO10AB — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: MCIMX6X3EVO10AB （同一形状・フットプリント） — 相違点: Core Architecture, Package, Mounting Type, Number of Cores, Ethernet.
クイック比較ツール — 並列比較する代替部品を選択:
MCIMX6X3EVN10AB
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MCIMX6X2EVN10AB
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MCIMX6X1EVK10AB
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MCIMX6X1EVK10AC
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MCIMX253CVM4
✅ ドロップイン✓ 在庫あり
$17.95 / 個
データシートを見る →MCIMX6X3EVO10AB 最大定格＆電気的特性
| Manufacturer | NXP Semiconductors |
| Series | i.MX 6SoloX |
| Core Architecture | ARM Cortex-A9 + ARM Cortex-M4 (heterogeneous) |
| Number of Cores | 2 (1x A9 + 1x M4) |
| Cortex-A9 Clock Speed | Up to 800 MHz (turbo to 1 GHz) |
| Cortex-M4 Clock Speed | Up to 227 MHz |
| Bus Width | 32-bit |
| パッケージ | 400-ball MAPBGA (17 mm x 17 mm) |
| 実装タイプ | Surface Mount, BGA |
| 動作温度範囲 | -40C to +105C (industrial / automotive AEC-Q100 grade) |
| GPU | Vivante GC400T |
| Display Resolution | Up to 1080p via LCDIF + IPU |
| Memory Interface | 16/32-bit DDR3 / DDR3L up to 800 MHz |
| Connectivity | Dual 10/100/1000 Ethernet (AVB), 2x USB 2.0, 3x SD/MMC, 2x CAN-FD, PCIe 2.0, UART, I2C, SPI, I2S |
| Security | ARM TrustZone, Secure Boot, HW AES/SHA/DES |
MCIMX6X3EVO10AB 400-ball mapbga (17 mm x 17 mm) ピン配置ガイド
MCIMX6X3EVO10AB (400-ball mapbga (17 mm x 17 mm) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: MCIMX6X3EVO10AB.
詳細は データシート をご参照ください。
主な用途
MCIMX6X3EVO10AB の用途: 8 件s: Automotive Infotainment Head Unit, Industrial HMI Control Panel, Telematics Control Unit (TCU), Smart Energy / IoT Gateway, Connected Home Hub, Medical Patient Monitor, Industrial Printer / Scanner Controller, Ruggedised Handheld Data Terminal.
Automotive Infotainment Head Unit
The MCIMX6X3EVO10AB's heterogeneous A9 + M4 pair is well suited to an automotive infotainment head unit: the Cortex-A9 runs Linux/QNX driving the LVDS display via the LCDIF/HDMDI path at up to 1080p with hardware-accelerated Vivante GC400T graphics, while the Cortex-M4 acts as a real-time watchdog handling CAN-FD body-network messages and audio sample-rate lock without OS jitter. The +105C Tj industrial/automotive temperature grade allows direct PCB placement inside the cabin head unit chassis, and ARM TrustZone + secure boot supports the OEM's content protection requirements for connected car services.
おすすめ
Industrial HMI Control Panel
For an industrial HMI panel needing both a responsive touch UI and deterministic fieldbus control, the MCIMX6X3EVO10AB lets designers run a Linux-based Qt/Web UI on the 800 MHz A9 while the 227 MHz M4 manages EtherCAT / PROFINET cycle timing through the dual 10/100/1000 Ethernet MAC with AVB/TSN support. This eliminates the historical split of MPU + MCU on the PCB, lowering BOM cost and shrinking the BOM footprint. The 400-MAPBGA's 17x17 mm form factor allows fan-less operation with a moderate copper-pour heatsink at typical 3-5 W SoC power dissipation for HMI workloads.
おすすめ
Telematics Control Unit (TCU)
A connected-car telematics control unit leverages the MCIMX6X3EVO10AB to run the LTE/Wi-Fi modem stack and OTA update agent on the Linux side (A9) while the M4 maintains the CAN-FD vehicle diagnostic link and eCall crash response with strict deterministic latency. The hardware crypto accelerators (AES / SHA / DES) and on-chip secure boot satisfy UN R155 / R156 cybersecurity requirements common in OEM connected-vehicle platforms. The dual-band Wi-Fi + LTE co-existence is supported by NXP's reference design with this SoC, including a designated UART path for the modem.
おすすめ
Smart Energy / IoT Gateway
Smart energy gateways often require aggregating multiple fieldbuses (Modbus, DLMS/COSEM, M-Bus, Wireless M-Bus) into a Linux application layer that talks to the cloud via Ethernet or LTE. The MCIMX6X3EVO10AB runs the metering app stack on the A9 and uses the M4 to manage the real-time metering sample acquisition at fixed 1 kHz without missing samples. The device's 32-bit DDR3 interface (up to 800 MHz / DDR3-1600) provides ample memory bandwidth for local caching of meter logs and cryptographic operations via the on-chip AES engine.
おすすめ
Connected Home Hub
A connected home hub needs simultaneous support for Wi-Fi/Bluetooth mesh, Zigbee or Thread border routing, and a Linux application layer running automation logic. The MCIMX6X3EVO10AB can run the Zigbee/Thread stack on the Cortex-M4 (real-time, 250 kbps symbol-rate critical) while the Cortex-A9 runs Node-RED or Home Assistant OS-grade automation software. The dual Ethernet + USB 2.0 + SD/MMC interface set covers typical home-hub I/O requirements without external bridges, and the part's industrial temperature grade accommodates unventilated cabinet mounting.
おすすめ
Medical Patient Monitor
For bedside patient monitors the MCIMX6X3EVO10AB's heterogeneous computing lets the M4 acquire vitals samples (ECG, SpO2, NIBP) with deterministic low jitter and immediately run the IEC 60601-1 alarm threshold logic, while the A9 runs a Linux-based Qt touch UI showing waveforms, trends, and HL7 messaging to the EMR. The hardware cryptographic engine accelerates TLS sessions to the EMR backend, and the dual CAN interfaces support hospital asset tracking buses. Although not directly AEC-Q100, the part's industrial/automotive temperature range supports indoor clinical environments.
おすすめ
Industrial Printer / Scanner Controller
An industrial label printer or document scanner can use the Cortex-M4 inside the MCIMX6X3EVO10AB to drive stepper motors for paper feeding / print head movement at deterministic microsecond-level timing, while the Cortex-A9 runs the embedded Linux image processing pipeline, OCR, and network protocol stack (LPR, IPP, REST). The dedicated 2D/3D GPU (Vivante GC400T) can accelerate image pre-processing such as image rectification, and the dual Ethernet ports allow simultaneous network connectivity and dedicated service-access VLAN segregation.
おすすめ
Ruggedised Handheld Data Terminal
Rugged handheld terminals for logistics, warehouse, and field service benefit from the MCIMX6X3EVO10AB's combined Linux app framework + deterministic M4 I/O control. The M4 can manage barcode imager triggering, keypad debouncing, and battery-charge monitoring without Linux latencies interfering. The Cortex-A9 runs the inventory application, Wi-Fi/cellular connectivity management, and display refresh on the LCDIF path. The industrial temperature grade plus the 400-MAPBGA solder-joint reliability required for drop/thermal-shock testing suits MIL-STD-810-style field-rugged designs.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: MCIMX6X3EVO10AB — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | MCIMX6X3EVN10AB | MCIMX6X2EVN10AB | MCIMX6X1EVK10AB | MCIMX6X1EVK10AC | MCIMX253CVM4 |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 400-ball MAPBGA (17x17 mm) | 400-ball MAPBGA (17x17 mm) - same | 400-ball MAPBGA (17x17 mm) - same | 400-ball MAPBGA (17x17 mm) - same | 400-ball MAPBGA (17x17 mm) - same | BGA-400 (footprint-compatible 17 mm class) - same |
| Core Architecture | 1x Cortex-A9 + 1x Cortex-M4 | 1x Cortex-A9 + 1x Cortex-M4 | 2x Cortex-A9 (DualLite) | 1x Cortex-A9 + 1x Cortex-M4 (6SLX) | 1x Cortex-A9 + 1x Cortex-M4 (6SLX) | 1x ARM926EJ-S (legacy i.MX25) |
| A9 Max Clock | 800 MHz (1 GHz turbo) | 800 MHz (1 GHz turbo) | Up to 1 GHz | 800 MHz class | 800 MHz class | 400 MHz (ARM926) |
| M4 Max Clock | 227 MHz | 227 MHz | N/A (DualLite has no M4) | 227 MHz | 227 MHz | N/A (no M4 in i.MX25) |
| GPU | Vivante GC400T | Vivante GC400T | Vivante GC320/GC880 | Vivante GC400T | Vivante GC400T | No integrated GPU |
| Memory Interface | 16/32-bit DDR3 / DDR3L up to 800 MHz | 16/32-bit DDR3 / DDR3L up to 800 MHz | 32-bit DDR3 / LPDDR2 | DDR3 / DDR3L | DDR3 / DDR3L | 16/32-bit mDDR / DDR2 (older) |
| Industrial / AEC-Q100 Temp Grade | Industrial / automotive qualified (extended) | Industrial grade same as target | Industrial grade same as target | Industrial grade | Industrial grade | Industrial / extended |
| Approx. 1k-piece Price (USD) | 19.20 | 20-22 (distributor range) | 22-28 | 22-25 | 22-25 | 12-18 (older silicon) |
主な差別化要因
- Heterogeneous A9 + M4 in a single SoC eliminates external MCU （vs MCIMX6X2EVN10AB)
- Same-package drop-in temperature grade flexibility （vs MCIMX6X3EVN10AB)
- Modern Vivante GC400T GPU vs legacy no-GPU silicon （vs MCIMX253CVM4)
設計ノート
Use NXP's 400-MAPBGA hardware design guide: 4-6 layer PCB with microvia stack-up is the minimum, and the 17x17 mm BGA pads require 0.4 mm pitch fan-out via dog-bone or via-in-pad. Estimated: at 0.4 mm pitch, microvia aspect ratio must stay under 0.75:1 to meet IPC-6012 Class 3 reliability. Keep continuous ground planes on layers 2 and 5 to provide return paths for the DDR3 byte lanes; this layout is critical for both SI and thermal spread.
Pair the MCIMX6X3EVO10AB with the NXP PCA9450 PMIC, which supplies all required i.MX 6 voltage rails (VDD_SOC, VDD_ARM, VDD_GPU, plus the DDR3 supply) in the correct sequencing order. Estimated: typical active power draw for SoC + DDR3 at A9 = 800 MHz, M4 = 100 MHz is 2.5-3.5 W; add 1.5 W headroom in the thermal envelope. The PMIC must be programmed via I2C using NXP-supplied OTP fuses to set the correct A9 voltage for the chosen OPP (overdrive point).
Estimated: with 8-10 W SoC peak power dissipation (worst case A9 + GPU + DDR3 active), the 400-MAPBGA theta_JA on a 4-layer JEDEC test board is roughly 18-22 C/W, meaning junction-to-ambient delta is on the order of 145-220 C at peak - so a heatsink or 6+ square inches of 2 oz copper pour on the top layer plus thermal via array under the centre 6x6 BGA ball cluster is mandatory for sustained workloads. Always validate by thermal probe under the worst-case application test pattern.
Do not power up the i.MX 6SoloX without programming the boot configuration (eFuses or external boot pins) - the default boot mode may try to source images from the SD card, which can collide with your SD/MMC storage. Also, ensure the DDR3ZQ calibration is performed at production; failures here are the most common cause of boot-time instability. Avoid using the M4 UART and a Linux UART on the same physical pins without mux discipline in the device tree.
DDR3 length-matching: per NXP's AN-5078 layout guide, byte-lane intra-pair skew must stay within 5 ps and inter-pair skew within 25 ps. Place the 32.768 kHz RTC crystal within 5 mm of the RTC_XTAL pins with a guarded ground island. Reference clock routing for the dual Ethernet MACs (ENET_REF_CLK, ENET_TX_CLK) should be length-matched, and the PCIe reference clock needs 100 ohm differential routing - any imbalance here causes functional PCIe enumeration failures.
コンプライアンス情報
RoHS / REACH per NXP product page disclosures. AEC-Q100 qualification status depends on specific ordering code variant - the EVO/EVN suffixes indicate temperature grade, not the AEC-Q100 stress level; consult NXP documentation. Halogen-free and conflict-mineral reports are not surfaced in the verified web data and are marked unknown.
