MPC860DPZQ66D4 - 66MHz PowerQUICC MPU 357-PBGA | NXP
部品番号: MPC860DPZQ66D4 ⚠ ラストタイムバイ| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $39.5 | $39.50 |
| 10 | $35.55 | $355.50 |
| 100 | $31.6 | $3,160.00 |
| 250 | $28.44 | $7,110.00 |
| 500 | $25.28 | $12,640.00 |
MPC860DPZQ66D4 概要
An MPU (Microprocessor Unit) is an integrated circuit that contains the central processing unit of an embedded system. The PowerQUICC architecture integrates a PowerPC integer core with a separate RISC-based Communications Processor Module (CPM) that offloads networking and serial tasks. Within the broader IC hierarchy, the MPC860 belongs to: microprocessor -> MPU -> embedded processor -> PowerPC architecture -> 32-bit RISC -> integrated communications controller. This integration reduces system cost and BOM count in networking and telecom designs compared with a discrete CPU plus external MAC/PHY bridge.
Key features of the MPC860DPZQ66D4 include 4 Kbytes of instruction cache and 4 Kbytes of data cache with write-through capability, a multiply/accumulate (MAC) unit, a DRAM controller supporting up to 256 Mbytes of address space, and an integrated CPM supporting Ethernet (10 Mbps), HDLC/SDLC, UART, SCC, and SPI peripherals. The 3.3V I/O and core supply, combined with a 66 MHz bus, deliver sufficient throughput for SOHO routers, ISDN terminal adapters, and industrial serial concentrators of the late-1990s/early-2000s generation.
The MPC860 architecture uses a Harvard-style split cache and a dedicated CPM to handle time-critical serial protocols. The CPM offloads DMA-driven serial transfers from the PowerPC core, allowing the CPU to focus on routing, control-plane, and management software. Memory is glue-less DRAM-up to 16/32-bit EDO or page-mode-with on-chip bank-select logic, reducing external chip count. A 32-bit address bus provides 4 Gbyte logical space, of which up to 256 Mbytes is practical DRAM.
Typical applications include SOHO routers, ISDN terminal adapters, xDSL modems, industrial serial protocol converters, and embedded telecom controllers. According to the Freescale/NXP PowerQUICC hardware specifications document, the part targets designs where deterministic serial communication must coexist with general-purpose control software on a single chip.
When designing with this device, ensure the 3.3V supply rail is clean and decoupled per the hardware specifications. Note that this MPN is flagged 'Not For New Designs' by NXP; new designs should consider PowerQUICC II (MPC82xx) or QorIQ (P-series) families instead, while existing designs can continue to use the MPC860DPZQ66D4 as a long-term supply part.
This page synthesizes distributor pricing, drop-in alternatives from the MPC860 family, and practical design notes that are not aggregated in a single place by the manufacturer datasheet alone.
ドロップイン代替品: MPC860DPZQ66D4 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: MPC860DPZQ66D4 （同一形状・フットプリント） — 相違点: RoHS Status, Package / Case, Core Architecture, Operating Temperature, Processor Type.
クイック比較ツール — 並列比較する代替部品を選択:
MPC860DPZQ80D4
✅ ドロップイン✓ 在庫あり
$13.85 / 個
データシートを見る →MPC860DPZQ50D4
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MPC860DTCZQ66D4
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MPC860TCZQ66D4
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MPC860ENCZQ66D4
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MPC860DPZQ66D4 最大定格＆電気的特性
| Processor Type | MPC8xx PowerQUICC 32-Bit RISC MPU |
| Core | 1 Core, 32-Bit PowerPC |
| Operating Frequency | 66 MHz |
| Core / I/O Voltage | 3.3 V |
| L1 Instruction Cache | 4 Kbyte |
| L1 Data Cache | 4 Kbyte |
| Co-Processor / DSP | Communications Processor Module (CPM) |
| Ethernet | 10 Mbps (via CPM, Fast Ethernet not supported on DP variant) |
| DRAM Controller | Yes, up to 256 Mbyte addressable |
| Address Bus Width | 32-Bit |
| パッケージ / ケース | 357-Ball PBGA, 25 x 25 mm |
| Packaging | Tray |
| Lead-Free Status | Contains Lead |
| RoHS ステータス | Non-RoHS (legacy BGA, contains lead) |
| 動作温度 | 0C to +70C (commercial grade) |
| Part Status | Not For New Designs |
MPC860DPZQ66D4 ピン構成
| ピン A1 | A[0] — Address bus bit 0 |
| ピン B14 | D[0] — Data bus bit 0 |
| ピン C10 | TS — Transfer Start |
| ピン D5 | TA — Transfer Acknowledge |
| ピン E20 | TXD1 — SCC1 transmit data (CPM) |
| ピン F3 | RXD1 — SCC1 receive data (CPM) |
| ピン G18 | ETH_TXD — Ethernet transmit data |
| ピン H7 | ETH_RXD — Ethernet receive data |
| ピン J22 | TCK — JTAG clock |
| ピン K15 | TMS — JTAG mode select |
| ピン L1 | VDD — Core 3.3V supply |
| ピン M20 | VSS — Ground |
| ピン N12 | XTAL1 — Crystal oscillator input |
| ピン P4 | XTAL2 — Crystal oscillator output |
| ピン R19 | RESET — Hardware reset, active low |
| ピン B1 | IRQ0 — External interrupt 0 |
| ピン D22 | IRQ1 — External interrupt 1 |
| ピン F15 | BR — Bus request |
| ピン H25 | BG — Bus grant |
主な用途
MPC860DPZQ66D4 の用途: 7 件s: SOHO Router Control Processor, ISDN Terminal Adapter, xDSL Modem / Residential Gateway, Industrial Serial Protocol Converter, Embedded Telecom Controller, Print Server / Networked Imaging Controller, Point-of-Sale Terminal Backplane.
SOHO Router Control Processor
The MPC860DPZQ66D4's integrated 10 Mbps Ethernet MAC and four SCC channels make it well-suited for SOHO router control-plane duties where it handles routing table management, NAT, and serial-port control alongside the datapath. Its 66 MHz PowerPC core offers sufficient headroom for early-generation IPv4 forwarding and management-plane software, while the 357-PBGA package enables compact board designs. Placed on the motherboard as the main MCU with external PHY via MII, this part replaces a discrete CPU + MAC + serial controller trio.
おすすめ
ISDN Terminal Adapter
ISDN terminal adapters of the late-1990s used the MPC860DPZQ66D4 to terminate the BRI/U interface and provide packetized data to a host. The CPM's HDLC/SDLC channels natively handle ISDN D-channel signaling at 16 kbps while the SCC ports carry B-channel data. The 66 MHz core runs the protocol stack and management code without external CPU assist. Designers placed the device at the heart of the adapter with an ISDN transceiver chip connected over the serial channels.
おすすめ
xDSL Modem / Residential Gateway
Early xDSL modems leveraged the MPC860DPZQ66D4's Ethernet MAC and multiple serial controllers to bridge between the DSL PHY and the local Ethernet segment. The DRAM controller glues to a bank of EDO DRAM for packet buffering, and the CPM's DMA channels sustain DSL line rates without CPU intervention. At 66 MHz with 3.3V supply, the part sits comfortably in residential gateway thermal envelopes. It is often paired with an external DSL AFE connected via the serial peripheral channels.
おすすめ
Industrial Serial Protocol Converter
Industrial gateways need deterministic serial protocol handling - the MPC860DPZQ66D4's CPM is purpose-built for this with SCCs configurable for UART, HDLC, bisync, and transparent modes. The 66 MHz core runs protocol-conversion firmware while the CPM offloads DMA-driven framing, leaving CPU bandwidth for management tasks. The 357-PBGA package is ruggedized at board level for industrial temperature operation when paired with the appropriate family variant.
おすすめ
Embedded Telecom Controller
Compact telecom control cards used the MPC860DPZQ66D4 to handle T1/E1 framing and signaling alongside host-side processing. The CPM's TDM channel supports up to four T1/E1 lines, and the integrated Ethernet enables backhaul to a control-plane network. With the 66 MHz grade, latency-sensitive signaling software executes deterministically under interrupt load, making the part a workhorse for legacy PBX and access-node line cards.
おすすめ
Print Server / Networked Imaging Controller
Office print servers of the late-1990s embedded the MPC860DPZQ66D4 to receive network print jobs over Ethernet and stream them to a parallel port or SCSI interface. The CPM's parallel interface and SCCs handle printer-side protocols, while the Ethernet MAC receives the network traffic. The 66 MHz core is well-matched to the modest CPU demand of page-description-language interpretation for low-duty-cycle printers, and the 357-PBGA fits the compact print-server board footprint.
おすすめ
Point-of-Sale Terminal Backplane
POS terminals deployed in retail often used the MPC860DPZQ66D4 as a backplane controller, linking cash drawers, scanners, and receipt printers over serial SCCs while presenting an Ethernet uplink to the store network. The CPM handles deterministic scanner-trigger timing and printer handshakes, while the 66 MHz PowerPC core runs the terminal application. The legacy BGA package supports ruggedized POS chassis designs that prioritize reliability over lead-free compliance.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: MPC860DPZQ66D4 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | MPC860DPZQ80D4 | MPC860DPZQ50D4 | MPC860DTCZQ66D4 | MPC860TCZQ66D4 | MPC860ENCZQ66D4 |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 357-PBGA (25x25) | 357-PBGA (25x25) - same | 357-PBGA (25x25) - same | 357-PBGA (25x25) - same | 357-PBGA (25x25) - same | 357-PBGA (25x25) - same |
| Core Frequency | 66 MHz | 80 MHz (+21%) | 50 MHz (-24%) | 66 MHz (same) | 66 MHz (same) | 66 MHz (same) |
| Ethernet | 10 Mbps (DP variant) | 10 Mbps | 10 Mbps | None (TC variant) | None (TC variant) | 100 Mbps Fast Ethernet |
| Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Lead-Free / RoHS | Contains Lead / Non-RoHS | Contains Lead | Contains Lead | Contains Lead | Contains Lead | Contains Lead |
| Peripheral Mix (CPM) | DP: Ethernet + SCCs | DP (Ethernet + SCCs) | DP (Ethernet + SCCs) | DTC (extended SCCs, no Ethernet) | TC (no Ethernet) | EN (Fast Ethernet + extended peripherals) |
| Lifecycle Status | Not For New Designs | Not For New Designs | Not For New Designs | Not For New Designs | Not For New Designs | Not For New Designs |
| Param Match vs. This Part | 100% | 90% | 80% | 70% | 70% | 80% |
主な差別化要因
- 10 Mbps Ethernet integrated with full CPM channel mix （vs MPC860TCZQ66D4)
- 66 MHz speed grade balances throughput and power （vs MPC860DPZQ80D4)
- Same 357-PBGA package across the family （vs MPC860ENCZQ66D4)
- Mid-range speed grade （vs MPC860DPZQ50D4)
設計ノート
Estimated: at 3.3V VDD and 66 MHz with typical CPM activity, the MPC860DPZQ66D4 draws approximately 300-450 mA from the 3.3V supply, giving 1.0-1.5 W dissipation. Use a low-impedance 3.3V regulator and place decoupling capacitors (0.1 uF + 10 uF bulk) within 5 mm of every VDD/VSS pair, with multiple VSS balls stitched to a continuous ground plane for return-current integrity.
The 357-ball PBGA at 25x25 mm requires a 6-layer or 4-layer PCB with ball pads drilled to manufacturer-recommended geometry. Escape-route the inner-row balls through microvias to inner signal layers, and use the outer rows for power/ground to maximize decoupling. Maintain a continuous reference plane under the BGA for all high-speed address and data traces, and provide 4-6 ground balls per quadrant for return-path stitching.
Do not assume that all MPC860 ZQ-package variants are software- and pin-compatible - the DP, TC, EN, and DTC suffixes denote different peripheral mixes. Verify against the family ordering guide and the device ID register before reusing firmware. Also, the MPC860DPZQ66D4 contains lead and is not RoHS compliant; do not place it in designs targeting lead-free assembly. New designs should migrate to the PowerQUICC II MPC82xx family.
Address and data buses should be length-matched within 1 cm on the MPC860 to avoid bus-turnaround timing violations. Series-stem termination (22-33 ohm) at the MPC860 end of the bus improves signal integrity on heavily-loaded memory buses, and SDRAM/EDO DRAM clocks should be routed with a 50 ohm controlled-impedance trace and a short stub to avoid reflections. Refer to the PowerQUICC hardware specifications AC timing section for exact setup/hold margins.
コンプライアンス情報
Per verified distributor listings (DigiKey, Mouser), the MPC860DPZQ66D4 contains lead and is not RoHS compliant. AEC-Q100 not applicable for this MPU grade. Legacy part in 'Not For New Designs' lifecycle.
