MPC866TZP133A - MPC8xx PowerQUICC 133MHz BGA Processor | NXP
部品番号: MPC866TZP133A ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $35.2 | $352.00 |
| 100 | $31.8 | $3,180.00 |
| 500 | $28.5 | $14,250.00 |
| 1,000 | $25.4 | $25,400.00 |
MPC866TZP133A 概要
What is a PowerQUICC processor? PowerQUICC is a family of integrated communications processors that combine a Power Architecture CPU core with a dedicated Communications Processor Module (CPM) for protocol handling. The hierarchy is: PowerQUICC -> communications processor -> microprocessor (MPU) -> integrated circuit -> semiconductor. By offloading bit-level protocol work (Ethernet, ATM, HDLC, UART) into the CPM, the core is freed for control-plane software, which is why PowerQUICC parts dominated telecom routers, DSLAMs, and PBX equipment.
The MPC866 family adds several differentiating capabilities over the MPC860/862. Enhanced SAR (ESAR) mode provides improved ATM Operation, Administration and Maintenance (OAM) support, OAM Performance Monitoring, and multiple APC priority levels for QoS-aware traffic shaping. Four 10/100 Mbps Ethernet interfaces, two 10 Mbps Ethernet MACs, serial ATM, HDLC, transparent, and UART channels are supported by the CPM, enabling multi-port bridge/router designs without external PHY/mac ASICs.
The part operates from a 1.8 V core and 3.3 V I/O supply, with 5 V TTL-tolerant inputs on peripheral pins, easing migration from legacy 5 V logic. Memory controller hardware supports DRAM (up to 16 banks), SRAM, EPROM, Flash, and a 32-bit data bus with parity, allowing direct attachment of external program and packet memory. The device is specified over 0 °C to 95 °C ambient (commercial grade), making it suitable for controlled-environment networking and industrial platforms.
Typical applications include multi-port 10/100 Ethernet routers, xDSL CPE/DSLAM line cards, ISDN PRI/BRI gateways, T1/E1 channel banks, industrial control with serial networking, and legacy telecom backplane processor boards. The integrated CPM dramatically reduces bill-of-materials cost versus a CPU + external MAC/PHY approach.
When designing with the MPC866TZP133A, pay close attention to the 357-ball PBGA escape routing: the 1.0 mm ball pitch demands 4-layer or better PCBs with microvia stackups, and a solid GND plus split 1.8 V/3.3 V power plane is required. Decouple each Vdd/Vss pair with 0.1 µF and 10 µF capacitors placed within 3 mm of the balls. For new designs, also evaluate the MPC8360/MPC8313 successors and verify longevity/support status, as MPC8xx is in long-term support rather than active release.
ドロップイン代替品: MPC866TZP133A — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: MPC866TZP133A （同一形状・フットプリント） — 相違点: Operating Temperature, Core Architecture, RoHS Status, Number of Cores, Mounting Type.
クイック比較ツール — 並列比較する代替部品を選択:
MPC866TZP133A
✅ ドロップイン✓ 在庫あり
$25.4 / 個
データシートを見る →MPC866PZP133A
✅ ドロップイン✓ 在庫あり
$51.9 / 個
データシートを見る →MPC866TVR133A
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MPC859TVR133A
✅ ドロップイン✓ 在庫あり
$54.1 / 個
データシートを見る →MPC859TZP133A
✅ ドロップイン✓ 在庫あり
$41.2 / 個
データシートを見る →MPC866TZP133A 最大定格＆電気的特性
| Core Processor | MPC8xx Power Architecture (32-bit) |
| Core Speed | 133 MHz |
| External Bus Speed | 66 MHz |
| Number of Cores | 1 Core, 32-Bit |
| Co-Processors / DSP | Communications Processor Module (CPM) |
| Core Supply Voltage | 1.8 V |
| I/O Supply Voltage | 3.3 V (5 V TTL tolerant inputs) |
| Process Technology | 0.18 µm CMOS |
| パッケージ | 357-PBGA (25x25 mm, 1.0 mm pitch) |
| Ethernet MACs | 4 x 10/100 Mbps + 2 x 10 Mbps |
| RAM Controllers | DRAM (up to 16 banks), SRAM, EPROM, Flash |
| Graphics Acceleration | No |
| 動作温度 | 0 °C to +95 °C |
| Lead Free Status | Contains Lead |
| RoHS ステータス | Non-Compliant (contains lead - per datasheet) |
| Part Status | Obsolete |
| Packaging | Tray |
MPC866TZP133A 357-pbga (25x25 mm, 1.0 mm pitch) ピン配置ガイド
MPC866TZP133A (357-pbga (25x25 mm, 1.0 mm pitch) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: MPC866TZP133A.
詳細は データシート をご参照ください。
主な用途
MPC866TZP133A の用途: 7 件s: Multi-Port 10/100 Ethernet Router, xDSL CPE / DSLAM Line Card, T1/E1 Channel Bank and PBX Backplane, Industrial Serial Gateway / Protocol Converter, ISDN PRI/BRI Gateway, Legacy Telecom Backplane Processor, Set-Top Box / Embedded Linux Appliance.
Multi-Port 10/100 Ethernet Router
The MPC866TZP133A's four integrated 10/100 Ethernet MACs plus two 10 Mbps MACs deliver up to six switched Ethernet ports from a single chip, eliminating an external PHY/MAC ASIC. The 133 MHz Power Architecture core handles routing tables, NAT, and firewall code while the CPM offloads packet DMA and HDLC framing. With 1.8 V core and 3.3 V I/O power, board design is straightforward, though the 357-PBGA's 1.0 mm pitch demands microvia escapes for the Ethernet MII/RMII traces.
おすすめ
xDSL CPE / DSLAM Line Card
Embedded xDSL CPE modems and DSLAM line cards leverage the MPC866TZP133A's HDLC, transparent, and ATM AAL1/AAL2/AAL5 channels plus the ATM SAR with Enhanced SAR (ESAR) features for OAM and priority queuing. The CPM handles the ATM TC layer while the core runs PPPoE, PPPoA, and routing stacks. The 1.8 V/3.3 V split-rail with 5 V TTL tolerance lets the design connect directly to legacy xDSL front-end ICs without additional level shifters.
おすすめ
T1/E1 Channel Bank and PBX Backplane
T1/E1 channel banks and PBX backplane controllers rely on the MPC866TZP133A's multi-channel TDM interfaces, UTOPIA, and HDLC controllers in the Communications Processor Module. The 133 MHz core processes call control / signaling while the CPM manages per-channel bit manipulation, dramatically reducing CPU load versus a software-only solution. Operating temperature 0-95 °C matches climate-controlled central-office environments and supports long-life telecom deployments.
おすすめ
Industrial Serial Gateway / Protocol Converter
Industrial gateways converting between Modbus, Profibus, and Ethernet use the MPC866TZP133A's mix of UART, HDLC, and Ethernet MACs to translate between legacy fieldbus protocols and TCP/IP. The integrated DRAM controller (up to 16 banks) lets the device hold routing tables and protocol buffers without external memory. Compared with a discrete CPU+MAC, the single-chip solution reduces bill of materials and improves MTBF in factory environments.
おすすめ
ISDN PRI/BRI Gateway
ISDN Primary Rate Interface gateways use the MPC866TZP133A's TDM, HDLC, and transparent serial channels to terminate PRI/BRI links on the wire side and present Ethernet/IP on the LAN side. The 32-bit core handles Layer 3 routing and VoIP signaling, while the CPM manages D-channel LAPD and B-channel HDLC processing. Integrated DRAM and Flash controllers remove the need for an external memory controller ASIC.
おすすめ
Legacy Telecom Backplane Processor
Legacy telecom backplanes often retain ATM UTOPIA interfaces alongside TDM T1/E1 streams; the MPC866TZP133A's UTOPIA, multi-channel HDLC, and ATM SAR make it a single-chip backplane processor. The 0-95 °C spec covers the central-office ambient, and the 357-PBGA package routes 32-bit data plus dedicated UTOPIA/MPHY buses. The RoHS-non-compliant status means it is best used for repair/replacement of deployed systems rather than new Greenfield builds.
おすすめ
Set-Top Box / Embedded Linux Appliance
Mid-complexity set-top boxes and embedded Linux appliances (running Power Architecture Linux 2.4/2.6) historically used the MPC866TZP133A for its 133 MHz core, integrated DRAM controller, and Ethernet ports. The 357-PBGA is overkill for low-cost designs but is well-suited to multi-feature IP appliances needing multiple serial interfaces. For new designs, evaluate the i.MX family for better power efficiency.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: MPC866TZP133A — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | MPC866PZP133A | MPC866TVR133A | MPC859TVR133A | MPC859TZP133A |
|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 357-PBGA (25x25) | 357-PBGA (25x25) | 357-PBGA (25x25) | 357-PBGA (25x25) | 357-PBGA (25x25) |
| Core Speed | 133 MHz | 133 MHz | 133 MHz | 133 MHz | 133 MHz |
| External Bus Speed | 66 MHz | 66 MHz | 66 MHz | 66 MHz | 66 MHz |
| Core Architecture | PowerQUICC MPC866 (32-bit, 1.8V core) | PowerQUICC MPC866 (32-bit, 1.8V core) | PowerQUICC MPC866 (32-bit, 1.8V core) | PowerQUICC MPC859 (no ATM SAR) | PowerQUICC MPC859 (no ATM SAR) |
| ATM SAR | Enhanced SAR (ESAR) | Enhanced SAR (ESAR) | Enhanced SAR (ESAR) | None | None |
| Ethernet MACs | 4 x 10/100 + 2 x 10 Mbps | 4 x 10/100 + 2 x 10 Mbps | 4 x 10/100 + 2 x 10 Mbps | 4 x 10/100 + 2 x 10 Mbps | 4 x 10/100 + 2 x 10 Mbps |
| Operating Temperature | 0 °C to +95 °C | 0 °C to +95 °C | 0 °C to +95 °C | 0 °C to +95 °C | 0 °C to +95 °C |
| RoHS Status | Non-Compliant (Contains Lead) | Non-Compliant (Contains Lead) | Non-Compliant (Contains Lead) | Non-Compliant (Contains Lead) | Non-Compliant (Contains Lead) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Six integrated Ethernet MACs (4 x 10/100 + 2 x 10) （vs MPC860TCZR50)
- Enhanced SAR (ESAR) ATM features （vs MPC859TVR133A)
- 0.18 µm process with 1.8 V core （vs MPC860TVR50D4)
設計ノート
The 357-PBGA's 1.0 mm pitch requires 4-layer or higher PCB stackups with microvia (HDI) technology for fan-out. Use 0.8 mm laser-drilled microvias stacked in pairs for the inner rows. Allocate full split power planes: 1.8 V for the core, 3.3 V for I/O, with a co-incident GND plane beneath. Decouple every Vdd/Vss pair with a 0.1 µF X7R placed within 3 mm of the balls plus a 10 µF bulk per supply rail.
Power-up sequencing requires Vdd-core (1.8 V) to ramp before Vdd-IO (3.3 V). Use a power-good supervisor (e.g., TPS3808 or similar) to gate the I/O rail until the core rail is within spec. Add soft-start on both rails to limit inrush; the MPC866 specifies a maximum dV/dt. Estimated: at full load (1.8 V core + 3.3 V I/O), expect around 1.8-2.5 W total dissipation - copper pours of at least 6 cm² on the top layer are needed to stay below 95 °C ambient.
The 357-PBGA's theta_JA of roughly 18-22 °C/W (with adequate PCB copper) means the junction rises 25-55 °C above ambient at typical 2 W dissipation. Maximum junction is 125 °C; this gives about 70-100 °C of ambient headroom (vs 95 °C commercial spec). For confined-enclosure designs (DSLAM backplanes), use a 1 m/s forced-air airflow or specify the extended-temp MPC866 variant.
Avoid connecting the JTAG TDI/TDO pins directly to 5 V - although inputs are 5 V TTL tolerant, the JTAG TAP state machine can latch-up if held in test-logic-reset during power-up. Add a 10 kΩ pull-down on TRST (asserted low for normal operation). Also, unused Ethernet MACs should be left with their PHY interfaces tri-stated and clock inputs grounded - open pins draw excessive leakage current on the 0.18 µm process.
The 66 MHz external bus is the noisiest network on the board. Keep bus traces length-matched within ±0.5 inches (12 mm), use 33 Ω series-termination at the driver end, and isolate the bus using a guard trace tied to GND. Place the SDRAM chips on the same layer as the MPC866 with via-stub length kept under 0.5 mm to avoid reflections at 66 MHz.
コンプライアンス情報
Per distributor pages (DigiChip, DigiKey), 'Lead Free Status: Contains Lead; RoHS Status: RoHS'. RoHS is non-compliant; REACH, conflict minerals, and halogen-free data not stated in provided sources. AEC-Q100 not applicable - part is commercial-grade 0-95 °C.
