PCA9306H - Dual I2C/SMBus Voltage-Level Translator | TI
部品番号: PCA9306H ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $0.85 | $0.85 |
| 10 | $0.72 | $7.20 |
| 100 | $0.48 | $48.00 |
| 500 | $0.38 | $190.00 |
| 1,000 | $0.31 | $310.00 |
PCA9306H 概要
A voltage-level translator is an interface IC that safely connects digital signals operating at different supply voltages, for example a 1.8 V microcontroller I2C peripheral talking to a 3.3 V or 5 V sensor. Within the signal-chain hierarchy, the PCA9306H belongs to the level-translator family of interface ICs, positioned alongside I2C buffers, repeaters, and multiplexers. Because I2C is an open-drain bus, translation requires a bidirectional pass element rather than a directional buffer - exactly the architecture this device implements.
Key features include directionless bidirectional translation, an enable pin that puts both switch channels into a high-impedance state when LOW, and low ON-state resistance of the pass FET, which keeps propagation delay minimal. The wider VREF1 range of the PCA9306H (1.2 V to 3.3 V, versus 1.0 V to 3.6 V or lower-floor variants in the family) makes it suitable for modern low-voltage processors. It supports standard-mode (100 kHz), fast-mode (400 kHz), and fast-mode plus (1 MHz) I2C devices as well as SMBus systems.
Architecturally, the device is a pair of N-channel pass transistors with gate drive referenced to EN and the reference supplies. When EN is HIGH, SDA1/SCL1 connect to SDA2/SCL2; pulling either side low through its open-drain pull-up propagates the low to the other side, achieving the gate-threshold offset that produces the voltage shift. Because there is no active buffering, signal integrity is essentially transparent, with propagation delay dominated only by the switch Ron and external pull-up resistors.
Typical applications include connecting 1.8 V MCUs to 3.3 V or 5 V sensors and EEPROMs, translating between 3.3 V SMBus hosts and lower-voltage peripherals in servers and networking cards, and interfacing low-voltage FPGA or SoC I2C banks to 5 V legacy buses in industrial control systems.
For reliable operation, size the pull-up resistors on both sides of the translator according to the bus speed and bus capacitance; each side must have its own pull-up. Also note the 200 kOhm internal pass-gate resistance behavior at low VREF2 voltages when calculating rise times.
This page synthesizes distributor data, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
ドロップイン代替品: PCA9306H — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
PCA9306DCUT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LSF0102DCUR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
TCA39306DCUR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
PCA9306DC125
✅ ドロップイン📋 参考代替品（カタログ未掲載）
PCA9306D
✅ ドロップイン📋 参考代替品（カタログ未掲載）
PCA9306H 仕様
| 機能 | Dual bidirectional I2C/SMBus voltage-level translator |
| チャネル数 | 2 |
| VREF1 Supply Range | 1.2 V to 3.3 V |
| VREF2 Supply Range | 1.8 V to 5.5 V |
| Direction Control | None required (directionless) |
| Enable Input | Yes (EN, active-high) |
| Supported Bus Speeds | Standard-mode (100 kHz), Fast-mode (400 kHz), Fast-mode Plus (1 MHz), SMBus |
| 出力タイプ | Open-drain (I2C standard) |
| パッケージ | 8-VSSOP (DCT) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| ブランド | Texas Instruments |
PCA9306H ピン構成
| ピン 1 | VREF1 — Reference supply for side 1, 1.2 V to 3.3 V |
| ピン 2 | GND — Ground |
| ピン 3 | EN — Enable input, active HIGH |
| ピン 4 | VREF2 — Reference supply for side 2, 1.8 V to 5.5 V |
| ピン 5 | SCL2 — Serial clock, side 2 |
| ピン 6 | SDA2 — Serial data, side 2 |
| ピン 7 | SDA1 — Serial data, side 1 |
| ピン 8 | SCL1 — Serial clock, side 1 |
主な用途
PCA9306H の用途: 6 件s: Low-Voltage MCU to 3.3V/5V Sensor Interface, Server and Networking Card SMBus Management, Industrial 5V Legacy Bus Bridging, Battery-Powered Portable and Wearable Devices, FPGA and SoC I2C Bank Translation, Automotive Infotainment and Cluster Peripherals.
Low-Voltage MCU to 3.3V/5V Sensor Interface
The PCA9306H fits sensor interfacing for modern 1.8 V microcontrollers because its VREF1 range extends down to 1.2 V, covering the lowest common logic rails, while VREF2 reaches 5.5 V for legacy sensors and EEPROMs. In a typical circuit, VREF1 ties to the MCU's 1.8 V rail, VREF2 to the 3.3 V or 5 V sensor rail, with 4.7 kOhm pull-ups on both sides of SDA and SCL. Because the pass-FET adds essentially no propagation delay, full 400 kHz fast-mode timing is preserved even with typical bus capacitance of 100 pF to 200 pF. The EN pin allows the MCU to isolate the sensor bus during boot until rails are stable, preventing latch-up or bus hang conditions.
おすすめ
Server and Networking Card SMBus Management
Server BMCs, power-supply controllers, and optical-module management interfaces commonly mix 3.3 V SMBus hosts with lower-voltage peripherals, and the PCA9306H's 1.2 V to 3.3 V VREF1 range plus 1.8 V to 5.5 V VREF2 range covers these combinations in a single 8-pin VSSOP. Its SMBus compatibility makes it suitable for DIMM SPD, PSU telemetry, and QSFP module management buses where a directionless translator avoids the stuck-buffer problems of directional shifters. Because the device is simply a pass FET when EN is HIGH, arbitration and clock stretching pass through transparently. The EN input also permits hot-swap isolation: pull EN LOW to remove a faulted card from the shared management bus without power cycling.
おすすめ
Industrial 5V Legacy Bus Bridging
Many industrial systems still run 5 V I2C buses for reliability in noisy environments, while new controllers use 1.8 V or 3.3 V logic. The PCA9306H bridges these domains directly: VREF2 at 5 V feeds legacy peripheral rails, VREF1 at 3.3 V or lower connects to the new MCU. The translator's lack of a direction pin means multi-master arbitration on the industrial bus works without external control logic. Its 5.5 V maximum on VREF2 provides headroom above nominal 5 V rails with tolerance. Place the translator near the connector side of the board and keep pull-ups on each domain's local rail so a single domain can be powered down while the other remains active, with EN used to gate the connection.
おすすめ
Battery-Powered Portable and Wearable Devices
Wearables and battery-powered IoT devices frequently mix a 1.8 V sensor domain with a 3.3 V radio or memory domain, exactly the 1.8 V-to-3.3 V case the PCA9306H covers. The pass-transistor architecture draws no static direction-control current and presents minimal series resistance, keeping the bus energy budget small - important when total system budget is in the milliamp-hours. The EN pin supports aggressive power gating: the host de-asserts EN to float the bus and eliminate pull-up leakage through the translator when the sensor domain is off. The small 8-pin VSSOP footprint suits space-constrained PCBs under flex or rigid substrates in wearable form factors.
おすすめ
FPGA and SoC I2C Bank Translation
Modern FPGAs and SoCs expose I2C banks at 1.8 V or lower HSTLV levels, while board-management buses run at 3.3 V; the PCA9306H's VREF1 floor of 1.2 V covers even 1.2 V-assisted banks. The translator's transparent pass behavior preserves clock stretching used by PMBus devices on the management side, and its 1 MHz fast-mode-plus support matches the high-speed fan controllers and digital power telemetry common on FPGA boards. Place the device between the FPGA bank and the management connector, with 2.2 kOhm pull-ups on the 3.3 V side and 4.7 kOhm on the low-voltage side. The EN pin can be driven by bank power-good so the bus only connects when the FPGA I/O rail is alive.
おすすめ
Automotive Infotainment and Cluster Peripherals
Automotive head units and clusters combine 1.8 V SoC I2C domains with 3.3 V and 5 V peripherals such as touch controllers, EEPROMs, and backlight drivers. The PCA9306H's 1.2 V to 3.3 V VREF1 and 1.8 V to 5.5 V VREF2 ranges cover these mixed rails within one footprint, and the enable input supports the power-sequencing discipline automotive power trees require. Because the device is directionless, the shared I2C between SoC, display bridge, and touch MCU arbitrates naturally. Designers should verify the specific TI ordering suffix grade for their temperature requirements, since automotive deployments may call for the related PCA9306-Q1 variant rather than the standard H version for guaranteed AEC qualification.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: PCA9306H — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | PCA9306DCUT | LSF0102DCUR | TCA39306DCUR | PCA9306DC125 |
|---|---|---|---|---|---|
| Package | 8-VSSOP (DCT) | 8-VSSOP (DCT) - same | 8-VSSOP (DCT) - same | 8-VSSOP (DCT) - same | 8-VSSOP (DCT) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | NXP Semiconductors |
| Channels | 2 (SDA, SCL) | 2 (SDA, SCL) | 2 (SDA, SCL) | 2 (SDA, SCL) | 2 (SDA, SCL) |
| Direction Control | None (directionless) | None (directionless) | None (directionless) | None (directionless) | None (directionless) |
| Enable Pin | Yes (active-high EN) | Yes (active-high EN) | Yes (EN/OE) | Yes | Yes (active-high EN) |
主な差別化要因
- Extended low-side rail coverage down to 1.2 V （vs PCA9306DC125 (NXP))
- Lower cost for conventional I2C speeds （vs TCA39306DCUR)
- Price optimization within the same footprint （vs LSF0102DCUR)
設計ノート
Every side of the translator must have its own pull-up resistor because the PCA9306H uses a standard open-collector I2C configuration. Size pull-ups per bus capacitance: 2.2 kOhm to 4.7 kOhm for 400 kHz to 1 MHz buses with moderate capacitance, up to 10 kOhm for slow SMBus segments. Undersized pull-ups increase sink current; oversized ones lengthen rise time and limit maximum bus speed. Place pull-ups close to the host/controller side of each domain.
VREF2 doubles as the high-side reference that biases the internal pass-gate, so it must be present before or with VREF1 for translation to work. At low VREF2 voltages the internal pass-gate resistance rises (the NXP PCA9306 documentation notes behavior approaching 200 kOhm in low-side-referenced conditions), which slows edges - check rise-time budgets if running VREF2 near 1.8 V at 1 MHz. Use EN, driven by a power-good signal or GPIO, to keep the bus disconnected until both reference rails are stable.
Do not use the PCA9306H as a push-pull (CMOS) level shifter - it is designed only for open-drain buses such as I2C and SMBus. Push-pull signals will not pull the opposite side low correctly and can cause bus contention. Also, do not substitute a directional translator (for example TCA9416-style buffered parts) without redesigning direction control; TI E2E threads highlight that PCA9306's tiny propagation delay comes precisely from being a simple FET pass connection, and buffered substitutes change timing and multi-master behavior.
コンプライアンス情報
RoHS compliance and lead-free status typical for active TI products; verify REACH and halogen-free status on the TI product page for the specific ordering suffix.
