PI7C9X111SLBFDE - x1 PCIe-to-PCI Reversible Bridge | Diodes Inc
部品番号: PI7C9X111SLBFDE ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $17.65 | $17.65 |
| 10 | $15.89 | $158.90 |
| 100 | $13.42 | $1,342.00 |
| 500 | $11.85 | $5,925.00 |
| 1,000 | $10.5 | $10,500.00 |
PI7C9X111SLBFDE 概要
A PCI Express-to-PCI bridge is a specialized interface IC that converts transactions between the modern PCIe serial point-to-point protocol and the legacy parallel PCI bus, enabling legacy PCI cards (NICs, video capture, industrial I/O) to operate behind newer PCIe-only host chipsets. It sits within the broader taxonomy of interface ICs -> bus bridges -> protocol converters -> semiconductors, and is one of the few commercially active reversible bridge families in production. Compared with conventional PCIe-to-PCI bridges, the PI7C9X111SL adds bidirectional traffic support, allowing the legacy PCI device to expose memory or DMA windows to the PCIe host.
Key features highlighted on the PI7C9X111SL datasheet include compliance with PCI Express Base Specification 1.1, 32-bit/66 MHz conventional PCI bus support, REQ/L[3:2]/REVRSB pin-strap configuration, and an optional Clock Power Management mode entered via TM1 strap. The bridge supports PME#, INTx, and conventional PCI interrupt/clock request signaling for legacy adapter passthrough. Its small-footprint 128-LQFP makes it attractive for embedded single-board computers and industrial backplanes with tight board real estate.
The device uses a packetized split-transaction architecture to translate PCIe TLP packets into conventional PCI cycles, with internal buffering sized for the x1 link. The reversible bridge capability means the chip can also operate as a PCI-to-PCIe bridge (PCI primary side facing the host), which is uncommon and useful in adapter cards that need to expose a single PCIe endpoint while presenting legacy PCI bus timing upstream.
Typical uses are industrial drive-in backplanes, retrofit board adapters that need to expose a single PCIe endpoint while presenting legacy PCI bus timing upstream, and embedded SBCs continuing to host legacy add-in cards. The 128-LQFP package supports a common load of 60 trailing-combe CTPs, enabling cost-effective board assembly.
When designing with this part, ensure the upstream PCIe link is wired with proper AC coupling capacitors and 100-ohm differential impedance. The TM1 strap selection for Clock Power Management should be tied high or low through a 10k resistor at board level. The bridge requires a 100 MHz reference clock for the PCIe side and a PCI clock for the downstream bus - both must be present before PERST# de-assertion.
This page synthesizes distributor pricing, drop-in alternatives from Diodes Incorporated and competitors, and practical design notes not consolidated in the manufacturer datasheet. Compliance status and parametric proximity have been cross-checked against DigiKey, Mouser, Octopart, and the Diodes product page.
ドロップイン代替品: PI7C9X111SLBFDE — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: PI7C9X111SLBFDE （同一形状・フットプリント） — 相違点: Product Type, Package, Bridge Direction, PCI Bus Speed, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
PI7C9X111SLBFDEX
✅ ドロップイン✓ 在庫あり
$5.5 / 個
データシートを見る →PI7C9X111SLBQE
✅ ドロップイン📋 参考代替品（カタログ未掲載）
PI7C9X2G404SLBFDE
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →PI7C9X2G404SVAFDEEX
✅ ドロップイン📋 参考代替品（カタログ未掲載）
PI7C9X111SLE
✅ ドロップイン📋 参考代替品（カタログ未掲載）
PI7C9X111SLBFDE 最大定格＆電気的特性
| Product Type | PCI Express to PCI Bridge (Reversible) |
| 機能 | x1 PCIe to 32-bit/66 MHz PCI reversible bridge |
| PCIe Specification | PCI Express Base Specification 1.1 |
| PCI Bus Width | 32-bit |
| PCI Bus Speed | 66 MHz |
| PCIe Lanes | x1 |
| Bridge Direction | Forward and Reverse (reversible) |
| パッケージ | 128-LQFP (14x14 mm) |
| ピン数 | 128 |
| 実装タイプ | Surface Mount |
| Power Consumption | Very low (per Diodes product page) |
| Configuration Straps | REQ_L[3:2], REVRSB, TM1 (Clock Power Management) |
| RoHS ステータス | Compliant |
| Lead-Free | Yes |
PI7C9X111SLBFDE 128-lqfp (14x14 mm) ピン配置ガイド
PI7C9X111SLBFDE (128-lqfp (14x14 mm) パッケージ) のピン配置。 このパワーデバイスは、ゲート、ドレイン、ソース端子を備えています。非極性パッケージの場合、正確なピン1の向きとフットプリントの詳細については、メーカーのデータシートを参照してください。主な用途には、電源設計、モータ駆動、負荷スイッチングがあります。
詳細なピン配置データはありません: PI7C9X111SLBFDE.
詳細は データシート をご参照ください。
主な用途
PI7C9X111SLBFDE の用途: 7 件s: Industrial Single-Board Computer (SBC) with Legacy PCI, Retrofit Adapter Card: PCI Device Add-in to PCIe Hosts, Test and Measurement Instrumentation Backplane, Embedded Networking Appliance with Legacy NIC Support, Industrial Control and Automation Backplane, Medical Imaging Equipment with Legacy PCI Frame Grabbers, Point-of-Sale (POS) Terminal with PCI peripherals.
Industrial Single-Board Computer (SBC) with Legacy PCI
The PI7C9X111SLBFDE bridges the x1 PCIe upstream port of a modern SoC to a legacy 32-bit/66 MHz conventional PCI bus, enabling SBC designs that must retain backwards compatibility with industrial I/O cards. The reversible architecture allows the same hardware to be reused in adapter-card topologies where a single PCIe endpoint is exposed while presenting PCI bus timing upstream. With very low power consumption and the compact 128-LQFP (14x14) footprint, the part fits embedded SBC layouts where board real estate is at a premium.
おすすめ
Retrofit Adapter Card: PCI Device Add-in to PCIe Hosts
The PI7C9X111SLBFDE in reverse-bridge mode converts legacy 32-bit/66 MHz PCI peripherals into a single PCIe endpoint, enabling adapter cards that drop into modern PCIe-only slots. Engineers use the REQ_L[3:2]/REVRSB configuration straps to enable the reverse direction at PERST# de-assertion. This is critical for industrial retrofits where existing PCI investments cannot be replaced, such as video capture cards, data acquisition modules, and motion control cards.
おすすめ
Test and Measurement Instrumentation Backplane
The PI7C9X111SLBFDE supports 66 MHz conventional PCI bandwidth, sufficient for mid-speed data acquisition modules and instrumentation backplanes. The x1 PCIe link provides up to 250 MB/s in each direction, ample for PCI cards operating at 32-bit/66 MHz (peak 264 MB/s). The reversible feature lets engineers reuse the same bridge IC in both analyzer cards (PCIe-to-PCI) and PCIe expansion modules (PCI-to-PCIe) without redesign.
おすすめ
Embedded Networking Appliance with Legacy NIC Support
The PI7C9X111SLBFDE enables embedded networking appliances to support legacy 32-bit PCI NICs while using a current-generation SoC with only PCIe lanes. The reversible bridge design is helpful when the appliance needs to expose a PCIe endpoint upstream and a conventional PCI bus downstream. Low power consumption is critical for fanless networking hardware where thermal headroom is limited.
おすすめ
Industrial Control and Automation Backplane
The PI7C9X111SLBFDE provides a bridge between PCIe-capable PLC controllers and legacy 32-bit PCI motion control / servo driver cards. The 128-LQFP (14x14) footprint fits standard industrial backplane card pitches, and the part's low power simplifies thermally constrained cabinet designs. The bridge's PME# and clock request signal forwarding allows legacy PCI cards to participate in system power management.
おすすめ
Medical Imaging Equipment with Legacy PCI Frame Grabbers
The PI7C9X111SLBFDE bridges modern PCIe-equipped medical imaging SoCs to legacy 32-bit PCI frame grabber and video capture cards used in ultrasound and endoscopy systems. The reversible architecture lets OEMs reuse the same bridge across multiple product SKUs. The 128-LQFP (14x14) package fits the compact form factors typical of medical imaging carts and bedside units.
おすすめ
Point-of-Sale (POS) Terminal with PCI peripherals
The PI7C9X111SLBFDE bridges x1 PCIe from a POS terminal SoC to legacy 32-bit PCI peripherals such as cash drawer controllers, legacy printers, and magnetic-stripe readers. Low power consumption and the small 128-LQFP footprint fit the compact enclosures typical of POS terminals. The reversible feature helps OEMs that sell into multiple retail hardware platforms with varying upstream PCIe/PCI configurations.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: PI7C9X111SLBFDE — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | PI7C9X111SLBFDEX | PI7C9X111SLBQE | PI7C9X111SLE | PI7C9X2G404SLBFDE | PI7C9X2G404SVAFDEEX |
|---|---|---|---|---|---|---|
| Package | 128-LQFP (14x14) | 128-LQFP (14x14) - same | 128-LQFP (14x14) - same | 128-LQFP (14x14) - same | 128-LQFP (14x14) - same | 128-LQFP (14x14) - same |
| Brand | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated |
| Function | PCIe-to-PCI Reversible Bridge | PCIe-to-PCI Reversible Bridge | PCIe-to-PCI Reversible Bridge | PCIe-to-PCI Reversible Bridge | PCIe Gen2 Packet Switch | PCIe Gen2 Packet Switch |
| PCIe Specification | PCIe 1.1 (x1) | PCIe 1.1 (x1) | PCIe 1.1 (x1) | PCIe 1.1 (x1) | PCIe 2.0 | PCIe 2.0 |
| PCI Bus Support | 32-bit / 66 MHz | 32-bit / 66 MHz | 32-bit / 66 MHz | 32-bit / 66 MHz | None (PCIe switch) | None (PCIe switch) |
| Reversible Bridge | Yes (PCIe-to-PCI and PCI-to-PCIe) | Yes | Yes | Yes | N/A | N/A |
| Pin Count | 128 | 128 | 128 | 128 | 128 | 128 |
| RoHS Compliance | Yes | Yes | Yes | Yes | Yes | Yes |
主な差別化要因
- Reversible bridge architecture （vs PI7C9X2G404SLBFDE)
- x1 PCIe to 32-bit/66 MHz PCI （vs PI7C9X110BNBE)
- Compact 128-LQFP footprint （vs PI7C9X110BNBE)
設計ノート
The PI7C9X111SLBFDE is a mixed-signal interface IC with high-speed PCIe differential pairs (PETp/n, PERp/n) and 32-bit parallel PCI bus. Route the PCIe differential pairs with 90-ohm differential impedance (85-100 ohm acceptable per PCIe 1.1 spec) and maintain length matching within 5 mils. Place AC coupling capacitors (75 nF to 200 nF typical, 100 nF recommended) on each PCIe transmit pair as close to the IC pins as possible. The 32-bit PCI bus should be routed with 50-ohm characteristic impedance and length matched within 1 inch across the AD[31:0] and C/BE[3:0] groups.
Estimated: At 3.3V supply typical for PCI I/O and 1.0V-1.2V for core (per PCI Express 1.1 power requirements), power dissipation should remain under 1W for the PI7C9X111SLBFDE based on the 'very low power consumption' claim on the Diodes product page. Decouple each power pin with 0.1uF ceramic + 10uF bulk capacitance within 50mil of the pin. Use a ferrite bead to isolate digital switching noise from sensitive analog reference pins. Always check the datasheet section on power sequencing - the PERST# signal must be held until both PCIe reference clock and PCI clock are stable.
Do not confuse the PI7C9X111SLBFDE (PCIe-to-PCI bridge, 128-LQFP) with the PI7C9X2G404SLBFDE (PCIe Gen2 packet switch, same 128-LQFP package). Despite identical pin count, they serve fundamentally different functions and cannot be substituted without redesign. Also note that the TM1 strap (Clock Power Management) must be tied high or low through a 10k resistor at board level - leaving it floating may cause unpredictable behavior. The REQ_L[3:2] and REVRSB pins are sampled only at PERST# de-assertion, so configuration changes after link-up are ignored.
コンプライアンス情報
RoHS compliant per Diodes product page and DigiKey listing. AEC-Q100 not applicable - this is an industrial/commercial interface IC, not an automotive-qualified product.
