PN5120A0HN1 - Full NFC Frontend 13.56MHz Reader | NXP
部品番号: PN5120A0HN1 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $6.4 | $6.40 |
| 10 | $5.65 | $56.50 |
| 100 | $4.95 | $495.00 |
| 500 | $4.3 | $2,150.00 |
| 1,000 | $3.85 | $3,850.00 |
| 3,000 | $3.45 | $10,350.00 |
PN5120A0HN1 概要
A NFC frontend (also called an NFC controller or HF RFID reader IC) is the analog and protocol bridge between a host microcontroller and an external contactless antenna. It generates the 13.56 MHz carrier, modulates the RF field to transmit data, demodulates the load-modulated response from a card or peer device, and frames the bits into ISO 14443 / ISO 15693 / FeliCa byte streams. Frontends sit below the NFC stack ( NCI / NCI 2.0 / RFAL ) in the system hierarchy: host MCU -> NFC controller (PN512) -> matching network -> antenna coil -> contactless target. Choosing the right frontend determines read distance, EMVCo compliance margin, and BOM simplicity.
Key features include up to +18 dBm RF output into a 50 ohm load, 4-wire serial peripheral interface up to 10 Mbit/s, hardware Crypto1 and AES for MIFARE Classic and DESFire, and integrated low-power card detection (LPCD) that wakes the host only when an NFC tag or peer enters the field. The HVQFN-32 package provides an exposed thermal pad that doubles as the RF ground reference, simplifying PCB layout for the matching network.
Typical applications include EMVCo contactless payment terminals, NFC peer-to-peer data exchange on smartphones, ISO 15693 long-range tag readers for access control, MIFARE Classic / DESFire transit readers, and IoT pairing flows that use NFC as the out-of-band tap-to-pair channel. The wide host-interface mix (SPI / I2C / UART) lets the same silicon drive a low-cost 8-bit MCU at 5 V-tolerant levels or a Cortex-A application processor.
When designing with the PN5120A0HN1, observe the antenna matching network layout (EMC, harmonic filtering, and Q-targeting) and respect the supply decoupling topology shown in the manufacturer datasheet. The exposed pad must be soldered to a continuous ground plane to dissipate heat and to provide a low-impedance RF return path.
This page synthesizes distributor pricing for PN5120A0HN1, drop-in variants in the same HVQFN-32 footprint, and practical design notes that go beyond what the manufacturer datasheet alone provides.
ドロップイン代替品: PN5120A0HN1 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
PN5120A0HN1/C2,151
✅ ドロップイン📋 参考代替品（カタログ未掲載）
PN5120A0HN1/C1,151
✅ ドロップイン✓ 在庫あり
$4.18 / 個
データシートを見る →PN5120A0HN1/C2,118
✅ ドロップイン📋 参考代替品（カタログ未掲載）
PN5120A0HN1/C1
✅ ドロップイン📋 参考代替品（カタログ未掲載）
PN5120A0HN1/C2
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MFRC63002HN
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MFRC63102HN
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SLRC61002HN
✅ ドロップイン📋 参考代替品（カタログ未掲載）
PN5120A0HN1 仕様
| Product Type | NFC Frontend / HF RFID Reader IC |
| Operating Frequency | 13.56 MHz |
| Supported Protocols | FeliCa, ISO 14443 A/B, ISO 15693, MIFARE Classic, MIFARE DESFire, NFCIP-1 (Peer-to-Peer) |
| 電源電圧 | 2.5 V to 3.6 V |
| Host Interfaces | I2C, SPI (up to 10 Mbit/s), UART |
| パッケージ | HVQFN-32 (5 mm x 5 mm) with exposed pad |
| 実装タイプ | Surface Mount |
| RF Output Power | Up to approx. +18 dBm into 50 ohm (per datasheet) |
| Modulation / Demodulation | On-chip, supports ASK 8-30%, BPSK for NFCIP-1 |
| On-die Crypto | Crypto1 (MIFARE Classic), AES hardware accelerator |
| Low-Power Card Detection | Yes (LPCD) |
| 動作温度 | -30 C to +85 C (consumer grade variant) |
| MSLレベル | 1 |
| RoHS ステータス | Compliant |
| Lead-Free | Yes |
PN5120A0HN1 ピン構成
| ピン 1 | AVDD — Analog supply 2.5-3.6 V |
| ピン 2 | AVSS — Analog ground |
| ピン 3 | RX1 — Receiver input 1 |
| ピン 4 | RX2 — Receiver input 2 |
| ピン 5 | VMID — Mid-rail reference for receiver |
| ピン 6 | TVDD — Transmitter supply |
| ピン 7 | TVSS — Transmitter ground |
| ピン 8 | TX1 — Transmitter output 1 |
| ピン 9 | TX2 — Transmitter output 2 |
| ピン 10 | AUX — Auxiliary analog output |
| ピン 11 | OSCIN — 27.12 MHz crystal oscillator input |
| ピン 12 | OSCOUT — 27.12 MHz crystal oscillator output |
| ピン 13 | DVDD — Digital supply 2.5-3.6 V |
| ピン 14 | DVSS — Digital ground |
| ピン 15 | SDA — I2C data / SPI data I/O |
| ピン 16 | SCL — I2C clock / SPI clock |
| ピン 17 | I2C — I2C enable strap (high = I2C mode) |
| ピン 18 | INT — Interrupt output (active low) |
| ピン 19 | RESET — Reset input (active low) |
| ピン 20 | AUX1 — Auxiliary digital I/O 1 |
| ピン 21 | AUX2 — Auxiliary digital I/O 2 |
| ピン 22 | AUX3 — Auxiliary digital I/O 3 |
| ピン 23 | TXEN — Transmitter enable strap |
| ピン 24 | RXEN — Receiver enable strap |
| ピン 25 | SIGIN — Signal input for test / LPCD |
| ピン 26 | SIGOUT — Signal output for test / LPCD |
| ピン 27 | TCK — Test clock (JTAG) |
| ピン 28 | TMS — Test mode select (JTAG) |
| ピン 29 | TDI — Test data in (JTAG) |
| ピン 30 | TDO — Test data out (JTAG) |
| ピン 31 | NC — Not connected (per datasheet) |
| ピン 32 | EP — Exposed pad - thermal/ground |
主な用途
PN5120A0HN1 の用途: 6 件s: Access Control / Long-Range ISO 15693 Readers, MIFARE Classic / DESFire Transit / Ticketing Readers, NFC Peer-to-Peer Data Exchange (Smartphone Tap-to-Share), IoT Tap-to-Pair / Wi-Fi Handover Devices, Industrial Tool Identification and Traceability, Payment-Reader Reference / Evaluation Platforms.
Access Control / Long-Range ISO 15693 Readers
The PN5120A0HN1's integrated ISO 15693 reader mode supports read distances up to 1 m when paired with a properly tuned 13.56 MHz antenna coil, making it ideal for physical access control readers that need to detect credentials at a comfortable hands-free range. With hardware Crypto1 and AES on-die, the IC handles the entire air-interface and crypto stack without burdening the host MCU, freeing the application processor for door logic, audit logging and keypad handling. Drop-in variants like MFRC63002HN also fit access-control designs that only need ISO 14443 A/B, while staying on the same HVQFN-32 footprint.
おすすめ
MIFARE Classic / DESFire Transit / Ticketing Readers
The PN5120A0HN1 was designed around MIFARE Classic Crypto1 and DESFire AES, so transit gates, ticket validators and loyalty terminals can use it without an external secure element. Its on-die AES accelerator cuts the time per DESFire transaction from tens of milliseconds to single-digit ms, which directly raises throughput at peak hours. The 13.56 MHz analog frontend tolerates the wide temperature swings seen at outdoor turnstiles (-30 C to +85 C), and the HVQFN-32 footprint with exposed pad keeps the RF ground return short for EMC compliance.
おすすめ
NFC Peer-to-Peer Data Exchange (Smartphone Tap-to-Share)
The PN5120A0HN1 supports NFCIP-1 peer-to-peer mode at 13.56 MHz, allowing a printer, speaker or industrial HMI to exchange URLs, Wi-Fi credentials or Bluetooth pairing tokens when a smartphone is tapped. Compared to a bare ISO 14443 reader, the NFCIP-1 stack adds BPSK modulation at 847 kB and 169 kB sub-carriers and is fully handled by the on-chip state machine, so the host CPU only needs to forward the SNEP or LLCP payload over SPI. The same HVQFN-32 footprint eases layout inside slim consumer enclosures.
おすすめ
IoT Tap-to-Pair / Wi-Fi Handover Devices
Battery-powered IoT hubs, smart-home bridges and BLE speakers can use the PN5120A0HN1's Low-Power Card Detection (LPCD) to stay in a sub-10 uA sleep state until a phone enters the field. When the carrier amplitude rises, the IC interrupts the host which then performs NFCIP-1 handover to push Wi-Fi or BLE credentials in one tap, eliminating QR-code pairing flows. Operating from a single 3.3 V rail and integrating the matching-network drive, the IC is well suited to coin-cell or Li-ion designs that need <100 uA average draw.
おすすめ
Industrial Tool Identification and Traceability
Manufacturing lines, tool cribs and rental fleets tag each asset with ISO 15693 or MIFARE tags; the PN5120A0HN1's multi-protocol analog frontend reads both formats without a board respin, simplifying mixed-fleet rollouts. The IC's SPI host interface (up to 10 Mbit/s) keeps scan latency below 50 ms even with AES-protected DESFire tags, while the HVQFN-32 exposed pad handles continuous-reader thermal loads in 24/7 conveyor applications. Drop-in compatibility with MFRC63002HN (ISO 14443 only) lets designers right-size the BOM for single-protocol lines.
おすすめ
Payment-Reader Reference / Evaluation Platforms
While the PN5120A0HN1 is not itself EMVCo 3.x qualified, it is the reference NFC frontend used in many pre-certified evaluation boards and is ideal for proof-of-concept payment terminals before migrating to PN5180A0HN or CLRC663plus. Its 2.5-3.6 V supply range matches coin-cell and 3.3 V system-on-chip designs, while the HVQFN-32 footprint matches the reference antenna-matching network from the NXP datasheet. Engineers can therefore port reference firmware directly to production and minimize risk when the platform later moves to the EMVCo-qualified PN5180.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: PN5120A0HN1 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | PN5120A0HN1/C2,151 | PN5120A0HN1/C1,151 | MFRC63002HN | MFRC63102HN | SLRC61002HN |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | HVQFN-32 (5x5 mm) | HVQFN-32 (5x5 mm) - same | HVQFN-32 (5x5 mm) - same | HVQFN-32 (5x5 mm) - same | HVQFN-32 (5x5 mm) - same | HVQFN-32 (5x5 mm) - same |
| Operating Frequency | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz |
| Supply Voltage | 2.5 V to 3.6 V | 2.5 V to 3.6 V | 2.5 V to 3.6 V | 2.5 V to 3.6 V | 2.5 V to 3.6 V | 2.5 V to 3.6 V |
| ISO 14443 A/B Support | Yes | Yes | Yes | Yes | Yes | No (ISO 15693 only) |
| ISO 15693 Support | Yes | Yes | Yes | No | Yes | Yes |
| FeliCa Support | Yes | Yes | Yes | No | No | No |
| NFCIP-1 Peer-to-Peer | Yes | Yes | Yes | No | No | No |
| On-die Crypto1 / AES | Yes (Crypto1 + AES) | Yes | Yes | Yes (Crypto1) | Yes (Crypto1) | Yes (Crypto1) |
| 1 pc Price (USD, 2026-10-20) | 6.40 | approx. 6.40 | approx. 6.40 | approx. 4.20 | approx. 4.80 | approx. 5.10 |
主な差別化要因
- Only HVQFN-32 family member with full FeliCa + NFCIP-1 P2P + AES support （vs MFRC63002HN)
- Broader protocol coverage than the MFRC63x series （vs MFRC63102HN)
- Same HVQFN-32 footprint as the SLRC610 family （vs SLRC61002HN)
設計ノート
Keep the 13.56 MHz antenna matching network within 5 mm of TX1/TX2 and RX1/RX2 to limit radiated parasitic coupling. Route the AVDD trace as a star from the ferrite bead to pin 1 and place the 100 nF + 1 uF ceramic decoupling pair within 2 mm of the supply pins; the exposed pad must be soldered to a continuous, low-impedance ground pour that spans at least the area of the package for thermal relief and RF return.
Do not drive the PN5120A0HN1 from a noisy 5 V USB rail - even with an LDO, residual switching ripple above 1 MHz will leak through the receiver and degrade ISO 14443 load-modulation sensitivity. Use a dedicated 3.3 V LDO with at least 60 dB PSRR at 1 MHz and place a pi-filter (ferrite + 1 uF + 100 nF) on the analog supply. Always reset the part by holding RESET low for at least 100 ns after both supplies are stable, otherwise the firmware initialization register reads can return garbage.
EMC compliance at the 13.56 MHz fundamental and its 27.12 MHz / 40.68 MHz harmonics requires harmonic filtering on the antenna coil - typically a 470 pF / 100 pF / 68 pF capacitor ladder - and a ground-shielded antenna loop. Estimated: at 13.56 MHz into a 50 ohm load the harmonic amplitude of the 2nd harmonic drops about 20 dB per filter stage; verify against your country's radiated emissions limit with a near-field probe before certification.
コンプライアンス情報
RoHS / REACH compliant per NXP product page and DigiKey product attribute listing. Not AEC-Q100 qualified - PN5120A0HN1 targets consumer / industrial NFC reader designs rather than automotive. Halogen-free status not confirmed in the verified web data - set to unknown.
