PN5120A0HN1/C1,151 - 13.56MHz NFC Frontend HVQFN-32 | NXP
MPN: PN5120A0HN1/C1,151 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6.42 | $6.42 |
| 10 | $5.78 | $57.80 |
| 100 | $5.15 | $515.00 |
| 500 | $4.62 | $2,310.00 |
| 1,000 | $4.18 | $4,180.00 |
PN5120A0HN1/C1,151 Overview
What is an NFC frontend? An NFC frontend (near-field communication frontend) is a dedicated transceiver IC that handles the 13.56 MHz inductive coupling and protocol framing between an MCU host and an external antenna. Within the system hierarchy it sits below the application processor and above the discrete matching/EMC network, classifying as an RF interface IC inside the broader RFID/NFC product family. The PN512 family, according to NXP's product page, powers more than 10 billion NFC transactions per year, making it the most broadly adopted NFC frontend on the market.
Key features include a built-in data mode detector that auto-selects between FeliCa, ISO 14443-A/B, and NFCIP-1 peer-to-peer modes, a 64-byte TX/RX FIFO buffer to offload the host, and a low-power standby mode drawing roughly 10 µA when the RF field is dormant. The integrated timer unit removes the need for an external watchdog, and the on-chip crypto coprocessor accelerates MIFARE Classic CRYPTO1 operations.
Architecturally, the PN5120A0HN1/C1,151 uses a direct-conversion receiver with I/Q demodulation, giving high input sensitivity down to roughly -42 dBm into a 50 Ω matched antenna. The on-chip PLL synthesizes the 13.56 MHz carrier from a 27.12 MHz crystal reference, and the transmitter delivers up to 230 mW into a matched coil at 5 V TVSS, covering the typical 5-7 cm read range required for payment terminals and access control.
Typical applications include contactless payment terminals (POS terminals supporting Visa payWave and Mastercard PayPass), access control readers, public-transit fare-collection terminals, NFC peer-to-peer pairing links for Bluetooth/Wi-Fi handover, and industrial ISO 15693 inventory tag readers. The wide protocol coverage also makes it suitable for multi-mode readers that must accept both MIFARE Classic legacy cards and NFC Forum tags in the same antenna field.
When designing with the PN5120A0HN1/C1,151, the EMC matching network between the TX1/TX2 outputs and the antenna coil is critical: even small detuning can desensitize the receiver by 4-6 dB. Designers should follow the antenna design guide from NXP and reserve the exposed pad (EP) as the only ground reference; the 32-pad land pattern requires 4 thermal vias under the EP for proper heat-sinking at full output power.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for PN5120A0HN1/C1,151 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with PN5120A0HN1/C1,151 (same form factor and footprint) — differing in Host Interfaces, Operating Temperature, Package, Supported Protocols.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
PN5120A0HN1/C2,151
✅ Drop-In📋 Reference alternative (not in catalog)
PN5120A0HN1/C1,118
✅ Drop-In📋 Reference alternative (not in catalog)
PN5180A0HN/C1,151
✅ Drop-In📋 Reference alternative (not in catalog)
PN5120A0HN/C2,151
✅ Drop-In📋 Reference alternative (not in catalog)
PN5120A0HN/C1,151
✅ Drop-In📋 Reference alternative (not in catalog)
PN5120A0HN1/C1,151 Specifications
| Function | NFC/RFID Reader/Transponder IC |
| Frequency | 13.56 MHz |
| Supported Protocols | ISO 14443 A/B, ISO 15693, FeliCa, NFCIP-1 |
| NFC Forum Tag Types | Type 1, Type 2, Type 3, Type 4 |
| Supply Voltage | 2.5 V to 3.6 V |
| Host Interfaces | I2C, SPI, UART |
| Package | 32-VFQFN Exposed Pad (HVQFN-32) |
| Mounting Type | Surface Mount |
| Operating Temperature | -30C to +85C |
| TX Output Power | Up to 230 mW at 5 V TVSS (per datasheet) |
| Crystal Reference Frequency | 27.12 MHz |
| FIFO Buffer | 64 bytes TX/RX |
| Crypto Coprocessor | MIFARE Classic CRYPTO1 hardware accelerated |
| Data Mode Detector | Integrated (auto-detects FeliCa / ISO 14443 / NFCIP-1) |
| RoHS Status | Compliant |
PN5120A0HN1/C1,151 Pin Configuration
| Pin 1 | TX1 — Antenna driver output 1 (differential) |
| Pin 2 | TX2 — Antenna driver output 2 (differential) |
| Pin 3 | RXP — Receiver positive input |
| Pin 4 | RXN — Receiver negative input |
| Pin 5 | AVDD — Analog supply (3.3 V typical) |
| Pin 6 | AVSS — Analog ground |
| Pin 7 | DVDD — Digital supply (3.3 V typical) |
| Pin 8 | DVSS — Digital ground |
| Pin 9 | OSCIN — 27.12 MHz crystal input |
| Pin 10 | OSCOUT — 27.12 MHz crystal output |
| Pin 11 | RST — Reset input (active low) |
| Pin 12 | IRQ — Interrupt request output to host |
| Pin 13 | SCL — I2C clock / SPI clock |
| Pin 14 | SDA — I2C data / SPI data (MOSI/MISO) |
| Pin 15 | ADR — I2C address select / SPI chip select |
| Pin 16 | AUX1 — Auxiliary output 1 |
| Pin 17 | AUX2 — Auxiliary output 2 |
| Pin 18 | RX — Receiver I/Q output (demodulated) |
| Pin 19 | TVSS — Transmitter supply (5 V typical for max power) |
| Pin 20 | TVDD — Transmitter driver supply |
| Pin 21 | SIGIN — Signal input for testing |
| Pin 22 | SIGOUT — Signal output for testing |
| Pin 23 | PVDD — Pin for power decoupling |
| Pin 24 | PVSS — Pin for power decoupling |
| Pin 25 | NRST — Non-maskable reset |
| Pin 26 | DREQ — DMA request output |
| Pin 27 | DACK — DMA acknowledge input |
| Pin 28 | INT0 — Interrupt input 0 |
| Pin 29 | INT1 — Interrupt input 1 |
| Pin 30 | GND — Ground |
| Pin 31 | GND — Ground |
| Pin 32 | EP — Exposed thermal pad - must be soldered to ground plane with thermal vias |
Typical Applications
PN5120A0HN1/C1,151 is suitable for 7 applications: Contactless Payment Terminals, Access Control & Door Readers, Public Transit Fare Collection, NFC Peer-to-Peer Pairing, ISO 15693 Inventory & Library Tag Readers, Multi-Protocol Industrial Readers, Wearable NFC Pairing.
Contactless Payment Terminals
The PN5120A0HN1/C1,151 is the established NFC frontend for POS terminals supporting Visa payWave, Mastercard PayPass, and American Express ExpressPay schemes. Its 13.56 MHz carrier fully covers ISO 14443 A/B at 106/212/424/848 kbps bitrates required by EMVCo contactless kernels, while the integrated data-mode detector auto-selects between ISO 14443-A cards and FeliCa mobile wallets without host intervention. According to NXP, the PN512 family powers more than 10 billion NFC transactions per year, so firmware stacks validated for PCI PTS 4.x and EMVCo L1/L2 are already available. Designers typically place the part between the secure MCU and the antenna coil with an external EMC-matching network sized for a 5-7 cm read range.
Recommended
Access Control & Door Readers
Office and hotel door readers use the PN5120A0HN1/C1,151 because it supports both legacy MIFARE Classic (1k/4k) credentials and modern ISO 14443-4 DESFire EV2/EV3 cards on the same antenna field. The on-chip CRYPTO1 coprocessor accelerates MIFARE Classic authentication in under 5 ms, keeping the host MCU's load low and reducing door-unlock latency. The 2.5-3.6 V supply range directly supports battery-backed door readers (3 V lithium primary cells) as well as 3.3 V wired systems. The HVQFN-32 footprint fits the slim-line mullion-mount reader form factor common in European access-control hardware.
Recommended
Public Transit Fare Collection
Transit turnstile validators and bus-mounted card readers rely on the PN5120A0HN1/C1,151's broad protocol support to read closed-loop MIFARE Classic transit cards (e.g. London Oyster legacy, Hong Kong Octopus) as well as open-loop bank cards and EMV contactless tokens. The on-chip PLL locked to the 27.12 MHz crystal delivers a stable carrier even in the vibration-heavy bus-reader environment where mechanical stress modulates the antenna capacitance. Read-write transaction times of 30-50 ms for a MIFARE Classic 1k block read fit within the 200 ms gating window typical of turnstile flow rates, reducing faregate queue build-up during peak hours.
Recommended
NFC Peer-to-Peer Pairing
The PN5120A0HN1/C1,151 supports the NFCIP-1 peer-to-peer mode that Bluetooth and Wi-Fi pairing assistants use to exchange link credentials over the 13.56 MHz field. In a wireless speaker or headset, the NFC tap pairs with the phone and triggers a subsequent BLE handover, removing the manual Settings > Bluetooth menu steps. The 64-byte FIFO buffer holds the complete NFC-DEP payload (up to 254 bytes is fragmented automatically by the on-chip LLC layer), letting the host MCU stream the pairing payload without tight real-time constraints. Active Target and Active Initiator modes are both supported, covering all four NFC Forum device-class permutations.
Recommended
ISO 15693 Inventory & Library Tag Readers
Library self-checkout kiosks and pharmaceutical inventory scanners use ISO 15693 (vicinity, 13.56 MHz) tags because of their extended read range of up to 1 m. The PN5120A0HN1/C1,151 supports ISO 15693 in addition to ISO 14443, so a single reader module can interrogate both vicinity tags on books and proximity tags on employee ID badges. The integrated AGC loop maintains receiver sensitivity across the 30 dB dynamic range as tagged items move along the conveyor, reducing false-negative reads when stacks of books pass the antenna. Designers pair the PN5120A0HN1/C1,151 with a 50 mm x 50 mm antenna coil sized for the typical 30-50 cm vicinity read zone.
Recommended
Multi-Protocol Industrial Readers
Industrial handheld readers used in logistics, asset tracking, and manufacturing test must read multiple NFC tag families without reconfiguration. The PN5120A0HN1/C1,151's integrated data-mode detector auto-discovers the incoming protocol and routes the demodulated data to the host, eliminating polling-loop firmware overhead. The 27.12 MHz external crystal provides the frequency accuracy required by both ISO 14443 (100% amplitude modulation) and ISO 15693 (10% / 100% modulation depth) without per-protocol retuning. Operating from -30 to +85 C, the part is rated for factory-floor temperature swings, while the HVQFN-32 footprint with exposed pad handles continuous RF duty cycles in tethered industrial scanners.
Recommended
Wearable NFC Pairing
Smartwatches, fitness bands, and medical wearables increasingly embed NFC for tap-to-pair and tap-to-share workflows. The PN5120A0HN1/C1,151 fits wearables because its low standby current (a few microamperes when the RF field is dormant) preserves the multi-day battery life these devices promise; the host MCU can park the PN5120 in standby between user taps. The 32-pin HVQFN at 5 mm x 5 mm fits inside the tight volume budgets of 38 mm watch cases, and the 2.5 V minimum supply lets the part run directly from a single Li-ion cell without a boost converter. Designers typically pair it with a printed coil antenna on the watch back-cover to enable tap-to-pay and tap-to-share from the wrist.
Recommended
Recommended Products Summary
Engineering reference data for PN5120A0HN1/C1,151 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | PN5120A0HN1/C2,151 | PN5120A0HN1/C1,118 | PN5180A0HN/C1,151 |
|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | HVQFN-32 (Exposed Pad) | HVQFN-32 (Exposed Pad) - same | HVQFN-32 (Exposed Pad) - same | HVQFN-40 (Exposed Pad) |
| Carrier Frequency | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz |
| Supply Voltage Range | 2.5 V to 3.6 V | 2.5 V to 3.6 V | 2.5 V to 3.6 V | 2.7 V to 5.5 V (wider) |
| Supported Protocols | ISO 14443 A/B + ISO 15693 + FeliCa + NFCIP-1 | Same protocol stack | Same protocol stack | Same + ISO 18000-3 mode 3 |
| Host Interfaces | I2C + SPI + UART | I2C + SPI + UART - same | I2C + SPI + UART - same | I2C + SPI (no UART) |
| FIFO Buffer | 64 bytes | 64 bytes | 64 bytes | 256 bytes (4x larger) |
| Operating Temperature | -30C to +85C | -30C to +85C | -30C to +85C | -40C to +105C |
| RoHS Status | Compliant | Compliant | Compliant | Compliant |
Key Differentiators
- Highest installed-base NFC frontend with 10B+ annual transactions (vs PN5180A0HN/C1,151)
- Wider supply voltage range and lower minimum supply than nearest upgrade path (vs RC663PLPV1)
- Auto protocol detection via integrated data mode detector (vs MFRC52202HN1)
Design Notes
Per the NXP PN512 reference antenna design guide, the 4-layer PCB stack-up must keep the antenna coil trace on the top layer with a continuous ground plane on layer 2, separated by a 0.2 mm prepreg. The TX1/TX2 traces to the external matching network (L/C) must be kept under 5 mm length and matched to 50 ohm differential impedance. A continuous ground keep-out of 5 mm around the antenna coil on all copper layers is required to prevent detuning from parasitic capacitance to ground.
Estimated: at continuous 230 mW RF output power and 70 percent transmitter efficiency, the PN5120A0HN1/C1,151 dissipates roughly 100 mW as heat. With the HVQFN-32 theta_JA of approximately 35 C/W on a JEDEC EIA/JESD51 4-layer test board, junction temperature rise above ambient is about 3.5 C - well within the -30 to +85 C rating. However, in enclosed housings without airflow, designers should add 4 thermal vias under the exposed pad and bond it to a 10 mm x 10 mm copper pour to keep junction rise below 10 C.
Two common pitfalls when laying out a PN5120A0HN1/C1,151 board: (1) routing digital MCU traces across the antenna near-field, which couples noise into the receiver and desensitizes by 4-6 dB; (2) omitting the ferrite beads on TVDD, which allows transmitter switching noise to leak onto the analog 3.3 V rail. Keep digital signals at least 8 mm from the antenna coil, and place 600 ohm ferrite beads (Murata BLM18PG601) in series with TVDD and AVDD per the reference design.
The 27.12 MHz crystal reference must be a fundamental-mode AT-cut device with 8-20 pF load capacitance, placed within 5 mm of the OSCIN/OSCOUT pins. Use a guard ring tied to AGND around the crystal traces to prevent radiated emissions from coupling back into the antenna coil. If the crystal load capacitance is mis-sized, the PN5120A0HN1/C1,151 will produce frequency error exceeding the 50 kHz carrier tolerance required by ISO 14443, causing non-conformant reader behavior and failed EMVCo certification.
Federal FCC Part 15 and EU EN 300 330 emissions limits apply to 13.56 MHz intentional radiators using inductive coupling. Designers must add a 2-section LC low-pass filter on the antenna coil feeding the matching network to suppress harmonics above 30 MHz. NXP reference designs typically achieve 6 dB margin under EN 300 330 with a 220 pF X7R cap and 2.2 uH inductor in pi configuration; ferrite beads alone do not provide sufficient harmonic attenuation for CE/FCC compliance testing.
Compliance Information
RoHS compliant per NXP product page environmental information. Not AEC-Q100 qualified - PN5120A0HN1 is intended for consumer/commercial payment and access-control use, not automotive. Reach and conflict-minerals declarations available on NXP.com product environmental page.
