S1D13517F00A100 - SVGA LCD Controller with SDRAM | Epson
部品番号: S1D13517F00A100 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.45 | $18.45 |
| 10 | $16.92 | $169.20 |
| 100 | $14.5 | $1,450.00 |
| 500 | $12.78 | $6,390.00 |
| 1,000 | $11.2 | $11,200.00 |
S1D13517F00A100 概要
A video processing IC (also called a display controller, LCD controller, or graphics controller) is a semiconductor device that sits between a host processor and a flat-panel display, taking the host's drawing commands and rendering them into a refresh buffer that the panel can scan out. Within the broader hierarchy, it belongs to display driver ICs > video processing ICs > interface ICs > integrated circuits, and it is the typical bridge between an embedded MPU and an SVGA-resolution TFT LCD.
Key features include SVGA (800x600) maximum resolution support, integrated 2D BitBLT engine, hardware Picture-in-Picture window compositing, 8/16-bit indirect host bus interface, support for up to 16 MB external SDRAM, and an operating temperature range of -40 C to +85 C suitable for industrial environments. The QFP15 128-pin package exposes a wide parallel host bus, RGB/TTL panel interface, and SDRAM control signals in a single footprint.
The architecture combines a 16-bit internal data path, dedicated 2D acceleration for block moves and fills, and programmable timing generators for the panel. Compared to software-only frame-buffer approaches, the S1D13517F00A100 offloads the host CPU from scanout and composition duties, freeing MPU cycles for application code.
Typical applications include industrial HMIs, point-of-sale terminals, medical instrument displays, in-vehicle information panels, and office automation equipment where an MPU must drive an SVGA TFT without burning CPU cycles on screen refresh. The PinP and alpha-blend features also support security/surveillance overlays on top of a primary video source.
When designing with this part, place the external SDRAM on short, impedance-matched traces to minimize access latency, and use a four-layer PCB with a continuous ground plane under the QFP package to control switching noise on the parallel host bus. A bulk decoupling capacitor (>= 10 uF) plus a 0.1 uF ceramic near each VDD pin is recommended.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the Epson product datasheet, giving engineers a faster path to BOM selection for SVGA TFT designs.
ドロップイン代替品: S1D13517F00A100 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
S1D13517F00A100-90
✅ ドロップイン📋 参考代替品（カタログ未掲載）
S1D13517F00A200
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
S1D13506F00A
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
S1D13504F00A
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
S1D13L01F00A
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
S1D13517F00A100 仕様
| Device Function | External SDRAM LCD Controller (video processing IC) |
| Display Resolution Support | Up to SVGA (800 x 600) |
| Host Interface | 8/16-bit indirect parallel host bus |
| External Memory Support | Up to 16 MB SDRAM |
| Overlay Features | Picture-in-Picture (PinP) and alpha-blending (a-Blend) |
| 2D Acceleration | BitBLT engine (block move/fill) |
| CORE/PLL Supply Voltage (COREVDD/PLLVDD) | 2.5 V |
| I/O Supply Voltage (IOVDD) | 3.3 V |
| Supply Voltage Range | 2.5 V to 3.3 V |
| 動作温度 | -40 C to +85 C |
| パッケージ | QFP15 (128-pin, 14x14 mm) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant (per distributor listing) |
| Family | S1D135xx LCD controller family |
S1D13517F00A100 ピン構成
| ピン 1 | DB[0] — Host data bus bit 0 (8/16-bit indirect) |
| ピン 32 | DB[15] — Host data bus bit 15 (LSB of upper byte when 16-bit) |
| ピン 33 | AB[0] — Host address bus bit 0 |
| ピン 64 | CS# — Chip select (active low) for host bus |
| ピン 65 | RD# — Host read strobe (active low) |
| ピン 66 | WR# — Host write strobe (active low) |
| ピン 80 | COREVDD — 2.5 V core / PLL supply |
| ピン 96 | IOVDD — 3.3 V I/O supply |
| ピン 100 | SDCLK — SDRAM clock to external SDRAM |
| ピン 110 | FPDAT[0] — Panel RGB output data bit 0 |
| ピン 120 | FPVSYNC — Panel vertical sync to TFT |
| ピン 128 | GND — Ground reference (multiple pins tied) |
主な用途
S1D13517F00A100 の用途: 6 件s: Industrial Human-Machine Interface (HMI) Display, Point-of-Sale (POS) Terminal Display, Medical Instrument Display Panel, In-Vehicle Information / Infotainment Panel, Office Automation Equipment (Printer / Copier Control Panel), Security / Surveillance Video Overlay Display.
Industrial Human-Machine Interface (HMI) Display
The Epson S1D13517F00A100 is well-suited to industrial HMI panels because its SVGA (800x600) support, 128-pin QFP15 footprint, and -40 C to +85 C operating range meet the resolution and environmental demands of factory-floor touchscreens. The integrated 2D BitBLT engine offloads window redraws from the host MPU, leaving CPU cycles for PLC logic. With up to 16 MB external SDRAM, the controller can double-buffer full SVGA color frames while maintaining smooth 60 Hz refresh on the TFT. Placed between an industrial MPU (e.g. a Renesas RX or Microchip PIC) and a 10.4-inch SVGA TFT, the S1D13517F00A100 streamlines wiring and accelerates the GUI render path. Trade-off: at 3.3 V IO and 2.5 V core, the part needs two rails and careful decoupling near the QFP.
おすすめ
Point-of-Sale (POS) Terminal Display
POS terminals need crisp color graphics, fast screen updates, and a reliable industrial-temperature controller. The S1D13517F00A100's SVGA resolution drives 8.0- to 12.1-inch POS panels with full color depth, while its 2.5 V core / 3.3 V IO supplies are easy to derive from a 5 V POS rail using simple LDOs. The integrated alpha-blending (a-Blend) hardware lets the terminal overlay signature pads or pop-up dialogs over the live transaction view without CPU intervention. External SDRAM (up to 16 MB) handles layered UI frames for snappy cashier UX. The 128-pin QFP15 package is well-established in POS motherboard designs and easy to route on four-layer FR-4.
おすすめ
Medical Instrument Display Panel
Medical displays require SVGA-class resolution, low EMI, and stable operation across the 0-70 C clinical envelope. The S1D13517F00A100's hardware Picture-in-Picture (PinP) feature allows a clinician to overlay live patient vitals on a reference image without a software compositor, reducing code complexity and validation effort. Operating from -40 C to +85 C, the controller tolerates warming enclosures in bedside monitors. The 8/16-bit indirect host interface simplifies connection to medical-grade MPUs and FPGAs. Designers should note the part is not AEC-Q100 qualified, so automotive-medical crossovers need additional qualification work.
おすすめ
In-Vehicle Information / Infotainment Panel
Cabin-mounted displays for fleet telematics, two-wheelers, and aftermarket infotainment benefit from the S1D13517F00A100's wide temperature range (-40 C to +85 C) and 8/16-bit host bus that connects easily to automotive MPUs. The SVGA resolution drives 7-inch WVGA-style panels with rich HMI for navigation and HVAC. While the part itself is not AEC-Q100 qualified, the silicon is mature enough for cabin environments when paired with appropriate system-level qualification. The QFP15 128-pin package is straightforward to assemble and rework, which helps low-volume automotive aftermarket production. Trade-off: for full automotive safety-critical displays, an AEC-Q100 controller is required.
おすすめ
Office Automation Equipment (Printer / Copier Control Panel)
Office MFPs and copiers need an SVGA color control panel with snappy menu transitions. The S1D13517F00A100's 2D BitBLT engine accelerates menu scrolling, while alpha-blending produces soft keys and translucent dialogs without taxing the printer SoC. The 128-pin QFP15 footprint has been used across multiple Epson-controller generations, easing PCB reuse. External 16 MB SDRAM supports high-resolution preview thumbnails next to the live UI. A typical implementation pairs the S1D13517F00A100 with an external SDRAM, a 5 V to 3.3 V/2.5 V LDO pair, and a 7- to 10.4-inch TFT.
おすすめ
Security / Surveillance Video Overlay Display
Surveillance monitors and DVR/NVR front panels benefit from the S1D13517F00A100's hardware Picture-in-Picture feature, which can composite a thumbnail camera view over a primary full-screen feed without software compositing. The 8/16-bit indirect host interface accepts commands from video encoder ASICs and SoCs that produce H.264 streams. Up to 16 MB external SDRAM handles multiple PIP windows and on-screen display overlays simultaneously. Operating from -40 C to +85 C, the controller is suitable for outdoor-rated NVR boxes and security-room consoles. The 14x14 mm QFP15 footprint is easy to assemble in mid-volume security OEM lines.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: S1D13517F00A100 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | S1D13517F00A100-90 | S1D13517F00A200 | S1D13506F00A | S1D13504F00A | S1D13L01F00A |
|---|---|---|---|---|---|---|
| Brand | Epson | Epson | Epson | Epson | Epson | Epson |
| Package | QFP15 (128-pin, 14x14 mm) | QFP15 (128-pin, 14x14 mm) - same | QFP15 (128-pin, 14x14 mm) - same | QFP15 (128-pin, 14x14 mm) - same | QFP15 (128-pin, 14x14 mm) - same | QFP15 (128-pin, 14x14 mm) - same |
| Max Resolution | SVGA (800x600) | SVGA (800x600) | SVGA (800x600) | VGA-class (lower) | QVGA/VGA (lower) | QVGA/VGA (lower) |
| External SDRAM Support | Up to 16 MB | Up to 16 MB | Up to 16 MB | Up to 16 MB (family typical) | Lower (family typical) | Lower (family typical) |
| Host Bus | 8/16-bit indirect | 8/16-bit indirect | 8/16-bit indirect | 8/16-bit indirect (family typical) | 8/16-bit indirect (family typical) | 8/16-bit indirect (family typical) |
| Overlay Features | PinP + a-Blend | PinP + a-Blend | PinP + a-Blend | Reduced | Reduced | Reduced |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C (family typical) | -40 C to +85 C (family typical) | -40 C to +85 C (family typical) |
| Pinout/Param Match | 100% | 100% | 95% | 80% | 75% | 70% |
主な差別化要因
- Highest feature set in the S1D135xx family （vs S1D13504F00A)
- 16 MB external SDRAM buffer (vs 8 MB typical in older family members) （vs S1D13506F00A)
- Mature Epson S1D135xx pinout, broad distributor availability （vs S1D13L01F00A)
設計ノート
The S1D13517F00A100 needs two supplies: COREVDD/PLLVDD at 2.5 V and IOVDD at 3.3 V. Use a 10 uF bulk plus 0.1 uF ceramic decoupling pair at each VDD pin. CORE must ramp and stabilize before IOVDD to guarantee PLL lock; a supervisor or simple RC delay on the IO rail prevents latch-up at power-up. Estimated: with a 3.3 V/100 mA IO supply and 2.5 V/50 mA core, total controller power is roughly 0.46 W under typical SVGA refresh loads.
Use a four-layer PCB with a continuous ground plane directly under the 128-pin QFP15 to control simultaneous-switching noise on the parallel host bus. Route SDRAM traces (SDCLK, SDDQM, SDCAS#, SDRAS#, SDWE#, SDA[0:11]) with matched lengths (delta <= 50 ps) and a 50 ohm characteristic impedance. Place external SDRAM within 25 mm of the controller to keep timing margins intact; longer stubs force a derating of the SDRAM clock frequency.
Do not assume the S1D13517F00A100 has internal frame-buffer memory; it requires external SDRAM (up to 16 MB) for any meaningful display. Pin 1 (DB[0]) of the QFP15 is easily miscounted on a 14x14 mm package with 0.5 mm pitch - verify the pin-1 marker orientation against the Epson mechanical drawing before soldering. The part is not AEC-Q100 qualified, so do not use it in safety-critical automotive ECUs without additional system-level qualification.
Keep the RGB/TTL panel output traces (FPDAT[0:23], FPHSYNC, FPVSYNC, FPDE) away from the host bus to minimize crosstalk. Place a 33 ohm series resistor on each FPDAT line near the controller to dampen reflections on long panel cables. If the panel FPC exceeds 100 mm, increase the series resistance to 47 ohm and add a small buffer to restore rise time.
The 8/16-bit indirect host bus can toggle aggressively during screen updates. Place a 33 ohm source-series resistor on each DB and AB line near the S1D13517F00A100 to control edge rates. Use Vias-in-pad only on the thermal pad (if present) - avoid via stubs on SDRAM and host-bus traces, which add parasitic inductance that erodes timing margins at the SDRAM clock.
コンプライアンス情報
RoHS compliance per distributor listing (DigiKey). AEC-Q100 not qualified - do not use in safety-critical automotive ECUs without further system-level qualification. REACH, halogen-free, and conflict-mineral status not stated in the provided data and marked unknown.
