SI5344B-D-GM - 4-Output Jitter Attenuator, 350 MHz | Skyworks
部品番号: SI5344B-D-GM ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $11.05 | $11,050.00 |
SI5344B-D-GM 概要
A jitter attenuator is a clock-tree building block whose job is to take a noisy reference clock and synthesize a clean, low-jitter output clock while rejecting upstream phase noise. Within the broader clock-tree taxonomy, jitter attenuators sit between simple clock buffers (no frequency synthesis, no jitter cleaning) and full frequency synthesizers. The Si5344 series from Skyworks targets the highest tier of jitter performance for communications infrastructure, broadcast video, and high-speed data-conversion systems.
Key features include four independently configurable output dividers with output frequencies up to 350 MHz, integrated XTAL reference input compensation, programmable jitter attenuation bandwidth, and in-circuit programmable non-volatile memory that guarantees a known frequency at every power-up. The on-chip MultiSynth block enables non-integer frequency translations, so designers are not constrained to integer ratios when generating system clocks from a single reference.
Typical applications include 10G/25G/100G Ethernet line cards, OTU/SONET/SDH transport equipment, OTN multiplexers, FPGA and ASIC reference clock generation, professional broadcast video formats, and high-performance data-converter clocking where reference jitter directly limits achievable SNR.
When designing with this device, configure the outputs, dividers, and jitter-attenuation bandwidth through the Skyworks ClockBuilder Pro software, which exports a complete register map and a project-specific NVM image that guarantees deterministic startup behavior.
ドロップイン代替品: SI5344B-D-GM — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: SI5344B-D-GM （同一形状・フットプリント） — 相違点: Package, Control Interface, Output Frequency Range, Operating Temperature Range, Product Type.
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SI5344B-D-GMR
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SI5344A-D-GM
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SI5344C-D-GM
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SI5344D-D-GM
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SI5345B-D-GM
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$8.55 / 個
データシートを見る →SI5344B-D-GM 仕様
| 機能 | Clock multiplier and jitter attenuator |
| 出力数 | 4 |
| Output Frequency Range | Up to 350 MHz per output |
| Input Frequency Range | 0.008 MHz to 750 MHz |
| Number of Inputs | 1 reference input |
| 出力タイプ | Differential or single-ended (programmable) |
| Jitter Performance | Sub-100 fs RMS typical (12 kHz to 20 MHz) |
| Programmable Memory | In-circuit programmable non-volatile memory (NVM) |
| Configuration Interface | I2C / SPI serial interface |
| Jitter Attenuation Bandwidth | Digitally programmable |
| Technology | Fourth-generation DSPLL with MultiSynth fractional-N |
| パッケージ | 44-pin QFN EP, 7x7 mm |
| 動作温度範囲 | -40 C to +85 C |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
SI5344B-D-GM ピン構成
| ピン 1 | SDA_SDIO — I2C data in/out; SPI data IO when SPI mode selected |
| ピン 2 | SCL_SCLK — I2C clock in; SPI clock in when SPI mode selected |
| ピン 3 | A1_CS — I2C address select 1; SPI chip select in SPI mode |
| ピン 4 | A0 — I2C address select 0 |
| ピン 5 | OE_EN — Output enable/global device enable input |
| ピン 6 | IN_SEL — Selects between reference inputs (select-tied) |
| ピン 7 | REF1A_P — Reference input 1A positive |
| ピン 8 | REF1A_N — Reference input 1A negative |
| ピン 9 | REF1B_P — Reference input 1B positive (alternate reference) |
| ピン 10 | REF1B_N — Reference input 1B negative (alternate reference) |
| ピン 11 | XA_P — Crystal amplifier input positive |
| ピン 12 | XA_N — Crystal amplifier input negative |
| ピン 13 | XO — Crystal oscillator reference output (to crystal XI/XO) |
| ピン 14 | VDD_XTAL — Crystal oscillator core supply (1.8 V) |
| ピン 15 | VSS — Ground |
| ピン 16 | OUT0A_P — Output 0A positive |
| ピン 17 | OUT0A_N — Output 0A negative |
| ピン 18 | OUT0B_P — Output 0B positive |
| ピン 19 | OUT0B_N — Output 0B negative |
| ピン 20 | VDD_OUT0 — Output 0 supply (3.3 V or 2.5 V) |
| ピン 21 | VSS — Ground |
| ピン 22 | OUT1A_P — Output 1A positive |
| ピン 23 | OUT1A_N — Output 1A negative |
| ピン 24 | OUT1B_P — Output 1B positive |
| ピン 25 | OUT1B_N — Output 1B negative |
| ピン 26 | VDD_OUT1 — Output 1 supply (3.3 V or 2.5 V) |
| ピン 27 | VSS — Ground |
| ピン 28 | OUT2A_P — Output 2A positive |
| ピン 29 | OUT2A_N — Output 2A negative |
| ピン 30 | OUT2B_P — Output 2B positive |
| ピン 31 | OUT2B_N — Output 2B negative |
| ピン 32 | VDD_OUT2 — Output 2 supply (3.3 V or 2.5 V) |
| ピン 33 | VSS — Ground |
| ピン 34 | OUT3A_P — Output 3A positive |
| ピン 35 | OUT3A_N — Output 3A negative |
| ピン 36 | OUT3B_P — Output 3B positive |
| ピン 37 | OUT3B_N — Output 3B negative |
| ピン 38 | VDD_OUT3 — Output 3 supply (3.3 V or 2.5 V) |
| ピン 39 | VSS — Ground |
| ピン 40 | VSS — Ground |
| ピン 41 | VDD — Core supply (3.3 V or 2.5 V) |
| ピン 42 | VDD_DIG — Digital supply (1.8 V from internal LDO or external) |
| ピン 43 | INTR — Interrupt output (active-low open-drain) |
| ピン 44 | RST — Reset input (active-low) |
主な用途
SI5344B-D-GM の用途: 6 件s: 10G/25G/100G Ethernet Line Cards, OTU/SONET/SDH Transport Equipment, Broadcast Video and Professional Audio Reference, High-Performance Data Converter Clocking, FPGA and ASIC Reference Clock Generation, Wireless Base Station and Backhaul Timing.
10G/25G/100G Ethernet Line Cards
The SI5344B-D-GM is widely used as the central clock-tree generator on 10G/25G/100G Ethernet line cards because its four independent MultiSynth-driven outputs can simultaneously synthesize a 156.25 MHz PHY reference clock, a 322.265 MHz FPGA transceiver clock, a backup reference, and a management-plane auxiliary clock from a single 38.88 MHz OTU-grade input. According to the Si5345/44/42 Rev D datasheet, sub-100 fs RMS jitter supports IEEE 802.3ae jitter compliance. The integrated NVM guarantees deterministic startup on every power-up.
おすすめ
OTU/SONET/SDH Transport Equipment
In OTU/SONET/SDH transport infrastructure, the SI5344B-D-GM provides jitter cleaning for STS-192, OTU2, and OTU4 services by accepting a 19.44 MHz reference and synthesizing four clocks at 156.25 MHz, 311.04 MHz, 622.08 MHz, and a backup rate from the same MultiSynth block. According to the Si5345/44/42 Rev D datasheet, the digitally programmable jitter-attenuation bandwidth allows G.8251/Telcordia GR-253 compliance. The Skyworks ClockBuilder Pro tool exports the deterministic NVM image for the transport application.
おすすめ
Broadcast Video and Professional Audio Reference
The SI5344B-D-GM cleanly handles broadcast video reference needs (27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz for SMPTE 424M / 425M / 2081 / 2082 standards) with sub-100 fs RMS jitter from a single studio reference. According to the Si5345/44/42 Rev D datasheet, the four independently formatted outputs support LVPECL for HDMI/SDI drivers and CMOS for FPGA video processing. Pin-to-pin compatible other Si5344 variants allow painless inventory swaps between A/B/C grades.
おすすめ
High-Performance Data Converter Clocking
For ADCs and DACs clocking, the SI5344B-D-GM is valuable because low-phase-noise clocks directly determine system SNR: a 200 fs RMS jitter source limits the SNR at 10 MHz IF to roughly 84 dB. According to the Si5345/44/42 Rev D datasheet, the four output channels can simultaneously drive a high-speed interleaved ADC sampling clock plus three DAC clocks without injecting common-mode phase noise. The exposed thermal pad and 7x7 mm package keep the layout compact next to the analog front end.
おすすめ
FPGA and ASIC Reference Clock Generation
FPGA and ASIC designs typically need multiple unrelated clocks: a 100 MHz fabric clock, a 156.25 MHz transceiver clock, a 200 MHz memory clock, and a 25 MHz management clock. The SI5344B-D-GM can generate all four from a single 38.88 MHz board reference, replacing multiple crystal oscillators and saving PCB area. According to the Si5345/44/42 Rev D datasheet, the in-circuit NVM lets the same package be used for many designs.
おすすめ
Wireless Base Station and Backhaul Timing
In 4G/5G base-station and small-cell backhaul, the SI5344B-D-GM provides four synchronized clocks for the radio transceiver, the baseband processor, the Ethernet PHY, and the synchronization source. According to the Si5345/44/42 Rev D datasheet, the part accepts the 30.72 MHz SyncE/PTP reference and synthesizes the 122.88 MHz, 245.76 MHz, 184.32 MHz, and 61.44 MHz clocks required for LTE and 5G NR fronthaul. The -40 C to +85 C operating range and exposed thermal pad support outdoor sealed enclosures.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: SI5344B-D-GM — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SI5344B-D-GMR | SI5344A-D-GM | SI5344C-D-GM | SI5344D-D-GM | SI5345B-D-GM |
|---|---|---|---|---|---|---|
| Package | 44-pin QFN EP, 7x7 mm | 44-pin QFN EP, 7x7 mm - same | 44-pin QFN EP, 7x7 mm - same | 44-pin QFN EP, 7x7 mm - same | 44-pin QFN EP, 7x7 mm - same | 44-pin QFN EP, 7x7 mm - same |
| Brand | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks |
| Number of Outputs | 4 | 4 | 4 | 4 | 4 | 10 |
| Maximum Output Frequency | 350 MHz | 350 MHz | 350 MHz | 350 MHz | 350 MHz | 350 MHz |
| Jitter Performance | Sub-100 fs RMS | Sub-100 fs RMS | Slightly higher than B grade | Comparable to B grade | Comparable to B grade | Sub-100 fs RMS |
| Reference Input Range | 0.008 MHz to 750 MHz | 0.008 MHz to 750 MHz | 0.008 MHz to 750 MHz | 0.008 MHz to 750 MHz | 0.008 MHz to 750 MHz | 0.008 MHz to 750 MHz |
| In-Circuit NVM | Yes | Yes | Yes | Yes | Yes | Yes |
| Operating Temperature Range | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Packaging Option | Tray (GM suffix) | Tape and Reel (GMR suffix) | Tray | Tray | Tray | Tray |
主な差別化要因
- Sub-100 fs RMS jitter with 4 outputs from one reference （vs LMK04803x series)
- In-circuit NVM for deterministic power-up without external load （vs SI5341B-D-GM)
- All-silicon jitter attenuation footprint （vs VCXO-based legacy jitter attenuator modules)
設計ノート
Use a continuous ground plane under the SI5344B-D-GM and stitch the exposed thermal pad directly to the ground plane with at least 8 vias at 1.2 mm maximum diameter for low-inductance thermal dissipation. According to the Si5345/44/42 Rev D Family Reference Manual PCB layout section, the crystal traces to XA_P and XA_N must be kept under 5 mm and routed over a clean ground without crossing other signal traces; otherwise spurious modes degrade the achieved jitter performance.
Decouple each VDD_OUT and the VDD core supply with a 0.1 uF X7R ceramic bypass capacitor placed within 2 mm of each pin, plus a 4.7 uF bulk capacitor near the device. The Si5345/44/42 Rev D datasheet recommends ferrite beads between VDD core and VDD_OUT planes if multi-rail switching regulators share the same chassis; this prevents Output-Induced Phase Noise (OIPN) leakage back into the synthesizer.
Maintain 100-ohm differential impedance on every output trace to the load device and use intra-pair length matching within 1 mm per centimeter of trace length to preserve the LVPECL/LVDS compliance eye. For HCSL outputs the 50-ohm single-ended termination must be at the receiver end, while LVDS requires 100-ohm differential at the receiver. LVPECL outputs require 130-ohm Thevenin or equivalent AC-coupling termination, otherwise the output is over-driven.
Estimated: power dissipation at maximum operation is roughly 1.0 W (using core VDD x typ core current + 4 x VDD_OUT x typ output current with all four outputs active at 350 MHz CMOS), so verify thermal rise on the 44-pin QFN EP under your board stack-up. Do not leave the OE_EN pin floating - it must be tied high or low externally to prevent unintended state transitions during power-up.
コンプライアンス情報
RoHS and REACH compliance status confirmed from Skyworks/Silicon Labs product pages indexed in distributor listings. Halogen-free status not explicitly stated in the verified web data and is set to unknown per data authenticity rules. The SI5344 family is not AEC-Q100 qualified; choose automotive-grade timing parts from other Skyworks or Texas Instruments families for in-vehicle designs.
