SI5345B-D-GM - 10-Output Jitter Attenuator | Skyworks
部品番号: SI5345B-D-GM ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $13.5 | $13.50 |
| 10 | $12.15 | $121.50 |
| 100 | $10.8 | $1,080.00 |
| 500 | $9.45 | $4,725.00 |
| 1,000 | $8.55 | $8,550.00 |
SI5345B-D-GM 概要
A jitter attenuator is a clock-tree building block that takes a potentially noisy reference signal and produces an ultra-clean clock that meets strict phase-noise and jitter budgets. Within the broader timing hierarchy it sits above simple crystal oscillators (XO) and below fully integrated timing cards; the SI5345B family specifically targets applications where any-frequency flexibility and sub-100-fs-class jitter are required simultaneously, such as 10G/25G/100G Ethernet PHYs, OTN framer/mapper ASICs, and synchronous-Ethernet line cards.
Key features include any-output frequency from 0.001 MHz to 350 MHz, programmable output formats (LVCMOS, LVDS, LVPECL, HCSL, CML), digitally programmable jitter-attenuation bandwidth, and a fractional-feedback architecture that delivers true any-frequency synthesis without requiring external VCXO components. Each of the ten outputs can be set to different logic levels, divider ratios, and enable states through the serial interface, replacing multiple single-purpose oscillators and buffers on dense telecom boards.
The architecture combines a fourth-generation DSPLL core with ten independent MultiSynth fractional dividers, allowing each output to be tuned to non-integer ratios from a common reference without compromising phase noise. Internal loop-filter components, EEPROM-backed default configuration, and per-output skew adjustment further simplify board design while keeping the BOM small.
Typical applications include IEEE 1588 packet-clock synchronization, OTU2/OTU4 framer line cards, 100G optical module reference clocks, broadcast video reference generation, and FPGA transceiver reference clocking. The Skyworks ClockBuilder Pro software lets designers generate a register map for any combination of input/output frequencies and load it into the on-chip NVM so the device powers up configured.
When laying out the Si5345B, treat the exposed pad as the primary thermal and grounds return path, place both 1.8 V and 3.3 V decoupling within 2 mm of their respective pins, and keep output traces at matched lengths (within 25 mil) for LVDS/LVPECL pairs to preserve jitter performance at high toggle rates.
This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: SI5345B-D-GM — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: SI5345B-D-GM （同一形状・フットプリント） — 相違点: Package, Output Frequency Range, Configuration Interface, Function, MSL Level.
クイック比較ツール — 並列比較する代替部品を選択:
SI5345B-D-GMR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5345A-D-GM
✅ ドロップイン✓ 在庫あり
$27.5 / 個
データシートを見る →SI5345A-D-GMR
✅ ドロップイン✓ 在庫あり
$8.75 / 個
データシートを見る →SI5345A-D04594-GM
✅ ドロップイン✓ 在庫あり
$25.9 / 個
データシートを見る →SI5345A-D04594-GMR
✅ ドロップイン✓ 在庫あり
$18.1 / 個
データシートを見る →SI5344B-D-GM
✅ ドロップイン✓ 在庫あり
$11.05 / 個
データシートを見る →SI5345B-D-GM 仕様
| 機能 | 10-channel any-frequency jitter attenuator / clock multiplier |
| Output Frequency Range | 0.001 MHz to 350 MHz |
| 出力数 | 10 |
| Phase Jitter (RMS, typical) | 0.09 ps |
| 電源電圧 | 1.8 V / 3.3 V (core / IO) |
| Output Logic Formats | LVCMOS, LVDS, LVPECL, HCSL, CML |
| Control Interface | I2C / SPI (serial) |
| On-chip NVM | Yes (in-circuit programmable, powers up configured) |
| Jitter Attenuation Bandwidth | Digitally programmable |
| Technology | DSPLL (4th gen) + MultiSynth fractional dividers |
| パッケージ | 64-pin QFN Exposed Pad (9x9 mm) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
SI5345B-D-GM ピン構成
| ピン 1 | IN0 — Reference input 0 (differential pair, true) |
| ピン 2 | IN0# — Reference input 0 (differential pair, complement) |
| ピン 3 | IN1 — Reference input 1 (differential pair, true) |
| ピン 4 | IN1# — Reference input 1 (differential pair, complement) |
| ピン 5 | IN2 — Reference input 2 (differential pair, true) |
| ピン 6 | IN2# — Reference input 2 (differential pair, complement) |
| ピン 7 | — Reference input 3, single-ended/CMOS |
| ピン 8 | VDD_REF — 1.8 V reference supply |
| ピン 9 | GND — Ground |
| ピン 10 | SDA_SDO — Serial data (I2C data / SPI data out) |
| ピン 11 | A0_CS — I2C address / SPI chip select |
| ピン 12 | SCL_SCLK — Serial clock (I2C / SPI) |
| ピン 13 | A1 — I2C address bit 1 |
| ピン 14 | RST — Device reset (active low) |
| ピン 15 | I2C_SEL — I2C / SPI mode select (logic high = SPI) |
| ピン 16 | OE — Output enable (active high, shared) |
| ピン 17 | VDD_DIG — 1.8 V digital core supply |
| ピン 18 | GND — Ground |
| ピン 19 | OUT0 — Clock output 0 (multi-format) |
| ピン 20 | OUT0# — Clock output 0 complement (LVDS/LVPECL) |
| ピン 21 | VDDO0 — Output driver 0 supply (1.8 / 2.5 / 3.3 V) |
| ピン 22 | OUT1 — Clock output 1 |
| ピン 23 | OUT1# — Clock output 1 complement |
| ピン 24 | VDDO1 — Output driver 1 supply |
| ピン 25 | OUT2 — Clock output 2 |
| ピン 26 | OUT2# — Clock output 2 complement |
| ピン 27 | VDDO2 — Output driver 2 supply |
| ピン 28 | OUT3 — Clock output 3 |
| ピン 29 | OUT3# — Clock output 3 complement |
| ピン 30 | VDDO3 — Output driver 3 supply |
| ピン 31 | GND — Ground |
| ピン 32 | OUT4 — Clock output 4 |
| ピン 33 | OUT4# — Clock output 4 complement |
| ピン 34 | VDDO4 — Output driver 4 supply |
| ピン 35 | OUT5 — Clock output 5 |
| ピン 36 | OUT5# — Clock output 5 complement |
| ピン 37 | VDDO5 — Output driver 5 supply |
| ピン 38 | OUT6 — Clock output 6 |
| ピン 39 | OUT6# — Clock output 6 complement |
| ピン 40 | VDDO6 — Output driver 6 supply |
| ピン 41 | GND — Ground |
| ピン 42 | OUT7 — Clock output 7 |
| ピン 43 | OUT7# — Clock output 7 complement |
| ピン 44 | VDDO7 — Output driver 7 supply |
| ピン 45 | OUT8 — Clock output 8 |
| ピン 46 | OUT8# — Clock output 8 complement |
| ピン 47 | VDDO8 — Output driver 8 supply |
| ピン 48 | OUT9 — Clock output 9 |
| ピン 49 | OUT9# — Clock output 9 complement |
| ピン 50 | VDDO9 — Output driver 9 supply |
| ピン 51 | GND — Ground |
| ピン 52 | NC — Not connected (per datasheet) |
| ピン 53 | NC — Not connected (per datasheet) |
| ピン 54 | NC — Not connected (per datasheet) |
| ピン 55 | NC — Not connected (per datasheet) |
| ピン 56 | NC — Not connected (per datasheet) |
| ピン 57 | NC — Not connected (per datasheet) |
| ピン 58 | NC — Not connected (per datasheet) |
| ピン 59 | NC — Not connected (per datasheet) |
| ピン 60 | NC — Not connected (per datasheet) |
| ピン 61 | NC — Not connected (per datasheet) |
| ピン 62 | NC — Not connected (per datasheet) |
| ピン 63 | NC — Not connected (per datasheet) |
| ピン 64 | NC — Not connected (per datasheet) |
| ピン EP | ePAD — Exposed thermal pad - solder to ground for thermal dissipation |
主な用途
SI5345B-D-GM の用途: 6 件s: IEEE 1588 Packet-Network Synchronization, OTU/OTN Framer Reference Clocking, 100G/25G Optical Module Reference Clocks, Broadcast Video Reference Generation, FPGA Transceiver Reference Clocking, Test & Measurement Clock Reference.
IEEE 1588 Packet-Network Synchronization
The SI5345B-D-GM is well suited for IEEE 1588 boundary/slave clock implementations because its 0.09 ps RMS jitter and digitally programmable jitter-attenuation bandwidth allow precise trade-offs between wander filtering and lock time. In a typical packet-sync card it accepts a recovered Ethernet clock (1.544 MHz, 19.44 MHz, or 25 MHz), attenuates wander in the DSPLL loop, and re-creates clean EEC/SSU-grade outputs for the line interface. Each of the ten MultiSynth outputs can be set to any rate in the 0.001 MHz to 350 MHz range, so a single chip serves multiple line cards.
おすすめ
OTU/OTN Framer Reference Clocking
100G/200G OTN framer ASICs need ultra-clean, any-frequency reference clocks. The SI5345B-D-GM's 0.09 ps RMS jitter and LVDS/LVPECL outputs up to 350 MHz match the OTU2/OTU4 framer's reference-clock input requirements directly. Designers can route one SI5345B from a central chassis reference (e.g., Stratum-3E OCXO) to feed multiple framer ASICs and mappers at different line rates, eliminating several single-frequency XO/VCXO parts. Exposed-pad packaging also supports the multi-watt dissipation typical of multi-output timing ICs.
おすすめ
100G/25G Optical Module Reference Clocks
CFP2/QSFP28 optical modules require reference clocks in the 156.25 MHz and 322.265625 MHz range with strict phase-noise masks. The SI5345B-D-GM's MultiSynth architecture synthesizes these rates from a common 25 MHz TCXO reference with sub-100-fs jitter, well within the IEEE 802.3bm clause for optical-module reference jitter. The 64-pin QFN-EP footprint fits standard optical-module PCB layouts, and the per-output format selection (HCSL/LVDS) lets one device serve both the host-side and line-side serdes.
おすすめ
Broadcast Video Reference Generation
Broadcast studios need multiple black/burst/tri-level sync references fed from a single master clock. The SI5345B-D-GM's any-output capability supports 27 MHz, 74.25 MHz, 148.5 MHz, and 1.485 GHz-locked rates from one reference, simplifying sync-generator designs. With 0.09 ps RMS jitter, the resulting analog video path stays below SMPTE ST 2059-2 wander thresholds, and per-output skew adjustment eliminates the need for external delay lines in long cable runs.
おすすめ
FPGA Transceiver Reference Clocking
Modern FPGAs (Xilinx, Intel, Microchip polarfire families) require multiple reference clocks for transceivers, memory controllers, and PLLs. The SI5345B-D-GM delivers ten independently-set outputs up to 350 MHz from one reference, ideal for FPGA boards where each transceiver bank needs a different reference (e.g., 156.25 MHz for 10G, 122.88 MHz for CPRI, 100 MHz for memory controllers). The Skyworks ClockBuilder Pro tool generates the register map for any combination of input/output frequencies and programs the on-chip NVM.
おすすめ
Test & Measurement Clock Reference
Lab instruments (sampling scopes, BERTs, signal generators) require ultra-low-jitter, any-frequency references for calibration paths. The SI5345B-D-GM's 0.09 ps RMS jitter and any-frequency flexibility (1 Hz to 350 MHz) suit trigger and reference rails in modular instruments; per-output invert, skew, and disable controls simplify power sequencing. The exposed-pad package supports continuous-drive scenarios typical of benchtop instrument operation.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: SI5345B-D-GM — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SI5345B-D-GMR | SI5345A-D-GM | SI5344B-D-GM | SI5345A-D04594-GM |
|---|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Package | 64-pin QFN Exposed Pad (9x9 mm) | 64-pin QFN Exposed Pad - same | 64-pin QFN Exposed Pad - same | 64-pin QFN Exposed Pad - same | 64-pin QFN Exposed Pad - same |
| Number of Outputs | 10 | 10 | 10 (lower-cost variant) | 8 | 10 (custom NVM) |
| Output Frequency Range | 0.001 MHz to 350 MHz | 0.001 MHz to 350 MHz | 0.001 MHz to 350 MHz | 0.001 MHz to 350 MHz | 0.001 MHz to 350 MHz |
| RMS Phase Jitter (typical) | 0.09 ps | 0.09 ps | 0.09 ps | 0.09 ps | 0.09 ps |
| Packaging | Tray (GM) | Tape & Reel (GMR) | Tray (GM) | Tray (GM) | Tray (GM) |
| Output Logic Formats | LVCMOS, LVDS, LVPECL, HCSL, CML | Same set | Same set | Same set | Same set |
| Control Interface | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI |
| NVM Default Configuration | Customer-defined (blank before programming) | Same | Same | Same | Custom OEM frequency plan pre-loaded |
主な差別化要因
- Ten true any-frequency outputs in one package （vs SI5344B-D-GM)
- DSPLL + MultiSynth fractional architecture （vs SI5338C-A-GM (legacy PLL-based))
- Pre-loaded custom NVM image available （vs SI5345B-D-GMR (blank NVM))
設計ノート
Estimated: with 10 outputs at 250 MHz LVDS into 100-ohm differential loads, the SI5345B-D-GM dissipates roughly 0.7 W typical. The 64-pin QFN-EP theta_JA is approximately 25 C/W on a 4-layer JEDEC test board, yielding a 17 C rise above ambient - acceptable for telecom environments. Ensure the exposed pad is soldered to a continuous ground copper pour with at least 8 thermal vias to inner ground planes for reliable operation under all output-loading profiles.
Per the Si5345 datasheet, place 1.8 V and 3.3 V decoupling capacitors within 2 mm of their respective supply pins and use a 0.1 uF + 1 uF pair in parallel for broadband decoupling. Differential output traces should be length-matched within 25 mil, and the exposed pad must be soldered to a low-impedance ground plane with multiple thermal vias to maintain the rated jitter performance at 350 MHz LVDS outputs.
Power-up sequencing matters: bring up VDD_DIG (1.8 V core) first, then VDD_REF and VDDOx supplies. The SI5345B-D-GM has internal power-on-reset, but a cleanly monotonic ramp avoids spurious output toggles that could couple into adjacent high-speed serdes lanes. Add a 1 uF bulk capacitor near each VDDOx pin and verify with a 6 GHz scope that no glitches appear on the 1.8 V rail within 1 ms of enable.
Do not skip programming the NVM: the SI5345B powers up with a default I2C/SPI configuration that may not match your frequency plan; always use Skyworks' ClockBuilder Pro tool to generate the register map and burn it to NVM before depanel. Avoid driving the IN0/IN1 differential inputs single-ended below 100 MHz into noisy references - the DSPLL acquisition loop performs best with at least 10 MHz or a clean differential source.
コンプライアンス情報
RoHS/REACH compliant per Skyworks Si5345 product family datasheet; not AEC-Q100 qualified (telecom/industrial grade).
