SN74HC109 - Dual J-K Flip-Flop with Clear/Preset | TI
部品番号: SN74HC109 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $0.45 | $0.45 |
| 10 | $0.38 | $3.80 |
| 100 | $0.3 | $30.00 |
| 500 | $0.25 | $125.00 |
| 1,000 | $0.2 | $200.00 |
SN74HC109 概要
A J-K flip-flop is a sequential logic device that toggles its output based on the J and K inputs at the rising edge of the clock. It is a fundamental building block in digital electronics, used for counters, registers, and state machines. The SN74HC109 belongs to the 74HC family of high-speed CMOS logic, which combines the speed of LSTTL with the low power consumption of CMOS.
Key features include two independent flip-flops with preset (PRE) and clear (CLR) inputs, positive-edge triggering, and a typical propagation delay of 12 ns. The device operates from 2V to 6V, with a maximum quiescent current of 40 µA, making it suitable for battery-powered applications. The outputs can drive up to 10 LSTTL loads, ensuring compatibility with TTL logic.
The SN74HC109 uses high-speed CMOS technology, providing a balanced combination of speed and power efficiency. The positive-edge-triggered design ensures predictable timing behavior, while the asynchronous PRE and CLR inputs allow immediate setting or resetting of outputs regardless of clock state. This makes it ideal for applications requiring reliable state control.
Typical applications include digital counters, frequency dividers, shift registers, and control logic in industrial automation, consumer electronics, and communication systems. Its wide voltage range and low power consumption make it suitable for portable and battery-operated devices.
When designing with the SN74HC109, ensure proper decoupling of the power supply with a 0.1 µF capacitor near the VCC pin. Unused inputs should be tied to VCC or GND to avoid floating states. The setup and hold times must be respected to guarantee reliable operation.
ドロップイン代替品: SN74HC109 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
SN74HC109N
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SN74HC109D
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SN74HC109NSR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SN54HC109J
✅ ドロップイン📋 参考代替品（カタログ未掲載）
CD74HC109E
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
74HC109D
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
MC74HC109AD
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
SN74HC109 最大定格＆電気的特性
| Number of Channels | 2 |
| Logic Family | HC |
| Logic Type | J-K Flip-Flop |
| Triggering Type | Positive Edge |
| 出力タイプ | Complementary |
| Supply Voltage - Min | 2 V |
| Supply Voltage - Max | 6 V |
| Propagation Delay Time | 12 ns (typical) |
| Maximum Quiescent Current | 40 µA |
| Input Current | 1 µA (max) |
| Output Current | ±4 mA at 5 V |
| 動作温度範囲 | -40°C to +85°C |
| Package Type | 16-DIP (N), 16-SOIC (D), 16-SOP (NS) |
| 実装スタイル | Through Hole / SMD |
| RoHS | Compliant |
SN74HC109 ピン構成
| ピン 1 | 1CLR — Clear input for flip-flop 1 (active low) |
| ピン 2 | 1J — J input for flip-flop 1 |
| ピン 3 | 1K — K input for flip-flop 1 |
| ピン 4 | 1CLK — Clock input for flip-flop 1 (positive edge) |
| ピン 5 | 1PRE — Preset input for flip-flop 1 (active low) |
| ピン 6 | 1Q — Output Q for flip-flop 1 |
| ピン 7 | 1Qbar — Complementary output for flip-flop 1 |
| ピン 8 | GND — Ground |
| ピン 9 | 2Qbar — Complementary output for flip-flop 2 |
| ピン 10 | 2Q — Output Q for flip-flop 2 |
| ピン 11 | 2PRE — Preset input for flip-flop 2 (active low) |
| ピン 12 | 2CLK — Clock input for flip-flop 2 (positive edge) |
| ピン 13 | 2K — K input for flip-flop 2 |
| ピン 14 | 2J — J input for flip-flop 2 |
| ピン 15 | 2CLR — Clear input for flip-flop 2 (active low) |
| ピン 16 | VCC — Positive supply voltage |
主な用途
SN74HC109 の用途: 6 件s: Digital Counters, Frequency Dividers, Shift Registers, State Machines, Data Synchronization, Control Logic.
Digital Counters
The SN74HC109's J-K inputs allow easy toggle mode for binary counters. With a typical propagation delay of 12 ns, it can count at frequencies up to 40 MHz at 5V. Its wide voltage range (2V-6V) makes it suitable for both 3.3V and 5V logic systems. In a counter circuit, the Q output of each flip-flop drives the clock of the next, enabling ripple or synchronous counting. The preset and clear inputs provide asynchronous reset capability, essential for initializing counters to a known state. This makes the SN74HC109 ideal for frequency dividers, event counters, and time-base generators in industrial and consumer electronics.
おすすめ
Frequency Dividers
By connecting Q to J and Q-bar to K, the SN74HC109 toggles on each clock pulse, dividing the input frequency by 2. Cascading multiple flip-flops creates divide-by-2^n circuits. The device's high-speed CMOS technology ensures low power consumption, making it suitable for battery-powered frequency dividers in watches, timers, and communication systems. The positive-edge triggering provides clean transitions, reducing glitches. The wide operating voltage range allows direct interface with both TTL and CMOS logic levels. The SN74HC109's 12 ns propagation delay supports input frequencies up to 40 MHz, enabling precise frequency division in RF and digital applications.
おすすめ
Shift Registers
The SN74HC109 can be configured as a shift register stage by connecting the Q output to the D input of the next stage. Its J-K inputs allow both shift and parallel load operations. The device's low input current (1 µA max) minimizes loading on driving stages, and its high output drive (±4 mA) can drive multiple loads. The preset and clear inputs enable parallel loading and resetting, making it useful in serial-to-parallel converters and data storage. The wide voltage range and low power consumption make it ideal for portable instrumentation and data acquisition systems. The 12 ns propagation delay ensures high-speed shifting in applications like LED displays and communication interfaces.
おすすめ
State Machines
The SN74HC109 is ideal for implementing finite state machines (FSMs) in control logic. Its J-K inputs provide flexible state transitions, and the preset/clear inputs allow asynchronous initialization. The device's high-speed operation (12 ns propagation delay) enables fast state transitions, critical for real-time control systems. The wide voltage range (2V-6V) allows interfacing with various logic families. In an FSM, the flip-flop outputs represent the current state, and combinational logic determines the next state based on inputs. The SN74HC109's low power consumption makes it suitable for battery-powered controllers in automotive, industrial, and consumer applications.
おすすめ
Data Synchronization
The SN74HC109 can synchronize asynchronous data signals to a clock, ensuring stable sampling in digital systems. Its positive-edge triggering captures data at precise clock edges, reducing metastability issues. The device's setup and hold times are specified in the datasheet, allowing engineers to design reliable synchronization circuits. The wide voltage range and low input current make it compatible with various sensor and interface signals. The preset and clear inputs provide a means to force outputs to known states during initialization. This application is common in communication interfaces, data acquisition systems, and microcontroller peripherals where clean, synchronized data is essential.
おすすめ
Control Logic
The SN74HC109 is used in control logic circuits for sequencing, latching, and decision-making. Its J-K inputs allow implementation of various logic functions, and the preset/clear inputs provide immediate control. The device's high output drive (±4 mA) can directly drive LEDs, relays, or other logic gates. The wide operating voltage range (2V-6V) makes it suitable for both battery-powered and industrial systems. The low quiescent current (40 µA max) ensures minimal power consumption in standby modes. The SN74HC109's robust design and wide temperature range (-40°C to +85°C) make it reliable in harsh environments, such as automotive and industrial control panels.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: SN74HC109 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SN74HC109N | SN74HC109D | CD74HC109E | 74HC109D |
|---|---|---|---|---|---|
| Package | 16-DIP (N), 16-SOIC (D), 16-SOP (NS) | 16-DIP (N) | 16-SOIC (D) | 16-DIP (E) | 16-SOIC (D) |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | NXP Semiconductors |
| Supply Voltage Range | 2V to 6V | 2V to 6V | 2V to 6V | 2V to 6V | 2V to 6V |
| Propagation Delay (typ) | 12 ns | 12 ns | 12 ns | 12 ns | 12 ns |
| Max Quiescent Current | 40 µA | 40 µA | 40 µA | 40 µA | 40 µA |
| Output Drive | ±4 mA at 5V | ±4 mA at 5V | ±4 mA at 5V | ±4 mA at 5V | ±4 mA at 5V |
| Operating Temperature | -40°C to +85°C | -40°C to +85°C | -40°C to +85°C | -40°C to +85°C | -40°C to +85°C |
| RoHS | Compliant | Compliant | Compliant | Compliant | Compliant |
主な差別化要因
- Wide operating voltage range (2V to 6V) （vs 74HC109D (NXP))
- Multiple package options （vs 74HC109D (NXP))
- Military temperature range option (SN54HC109) （vs CD74HC109E)
設計ノート
Decouple the VCC pin with a 0.1 µF ceramic capacitor placed as close to the pin as possible. For high-speed operation, add a 10 µF electrolytic capacitor at the power entry point. The SN74HC109 has a maximum quiescent current of 40 µA, but dynamic current increases with frequency; ensure the power supply can handle the peak current during switching.
Keep clock and data traces short and avoid routing them parallel to each other to minimize crosstalk. Use a solid ground plane to reduce noise. For the 16-SOIC package, ensure proper thermal relief for the ground pins. Follow the layout guidelines in the TI application note 'Designing with Logic' for optimal performance.
Unused inputs (J, K, PRE, CLR) must not be left floating. Tie unused J and K to a defined logic level (VCC or GND) to prevent oscillation. PRE and CLR are active low; tie them to VCC when not used. Respect the setup and hold times specified in the datasheet to avoid metastability. Do not exceed the absolute maximum ratings of 7V on VCC.
コンプライアンス情報
RoHS compliant per TI product page. Not AEC-Q100 qualified.
