TDA8763AM/3/C5 - 10-Bit 30 MSPS Sigma-Delta ADC | NXP
部品番号: TDA8763AM/3/C5 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $6.5 | $6.50 |
| 10 | $5.85 | $58.50 |
| 100 | $5.2 | $520.00 |
| 500 | $4.65 | $2,325.00 |
| 1,000 | $4.1 | $4,100.00 |
TDA8763AM/3/C5 概要
A sigma-delta ADC is a converter architecture that oversamples the input signal at many times the Nyquist rate and uses noise shaping plus digital filtering to push quantization noise out of the signal band. The architecture belongs to the broader taxonomy of data converters (ADC -> Nyquist-rate or oversampling converter -> sigma-delta modulator -> integrated ADC IC -> semiconductor), enabling high effective resolution without requiring laser-trimmed component matching. The TDA8763AM/3/C5 supports DC-sampling operation and integrates the modulator plus decimation filtering on-chip.
Key features include 10-bit resolution, 30 MSPS sampling rate, single +5 V analog supply operation, low power consumption suitable for portable or thermally-constrained systems, and CMOS digital I/O for direct connection to ASICs, FPGAs, or DSPs. The device is one variant in the TDA8763AM family, which spans 30/40/50 MHz sampling-speed grades (TDA8763AM/3, /4, /5 respectively) sharing the same SSOP-28 pinout. The 'C5' suffix denotes the 30 MHz grade in tape-and-reel packaging.
Typical applications include digital video broadcast (DVB) IF digitization, CCD/CIS image sensor front ends, industrial process control, instrumentation, and intermediate-frequency sampling for communications receivers. The wide analog input bandwidth and DC sampling capability make it suitable for both baseband and IF signal chains.
When designing with this ADC, ensure that the analog input drive network provides the correct common-mode and termination load specified by the datasheet, and place the supply decoupling capacitors as close as possible to AVDD and AGND. Allow adequate PCB ground plane separation between the analog and digital grounds to avoid coupling switching noise into the analog front end. This page synthesizes distributor pricing, drop-in family variants, and practical design notes for the 30 MHz grade not found in a single source.
ドロップイン代替品: TDA8763AM/3/C5 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: TDA8763AM/3/C5 （同一形状・フットプリント） — 相違点: Architecture, DC Sampling, Package, Sampling Rate, Operating Temperature.
クイック比較ツール — 並列比較する代替部品を選択:
TDA8763AM/3/C4
✅ ドロップイン✓ 在庫あり
$6.5 / 個
データシートを見る →TDA8763AM/4/C5
✅ ドロップイン📋 参考代替品（カタログ未掲載）
TDA8763AM/5/C5
✅ ドロップイン✓ 在庫あり
$7.2 / 個
データシートを見る →TDA8763AM/3,118
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
TDA8763AM/4,118
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
TDA8763AM/3/C5 最大定格＆電気的特性
| 分解能 | 10 bit |
| サンプリングレート | 30 MSPS (C5 grade) |
| Number of Inputs | 1 |
| Architecture | Sigma-Delta |
| Analog Supply Voltage | 5 V |
| パッケージ | SSOP-28 (SOT341-1), 28 leads, 5.3 mm body width |
| 実装タイプ | Surface Mount |
| Data Interface | CMOS parallel |
| Sampling Family Grade | /3 = 30 MHz, /4 = 40 MHz, /5 = 50 MHz |
| 動作温度範囲 | -40 C to +85 C |
| Packaging | Tape & Reel (TR) - ,118 suffix |
| DC Sampling | Allowed (per datasheet) |
| Lead-Free / RoHS | Compliant |
| Family | TDA8763AM (high-speed low-power ADC series) |
TDA8763AM/3/C5 ピン構成
| ピン 1 | VDDA — Analog supply voltage (5 V) |
| ピン 2 | VSSA — Analog ground |
| ピン 3 | VIN — Analog input |
| ピン 4 | VSSA — Analog ground |
| ピン 5 | VDDA — Analog supply voltage (5 V) |
| ピン 6 | VREF — Reference voltage decoupling |
| ピン 7 | VSSA — Analog ground |
| ピン 8 | CLK — Clock input |
| ピン 9 | VDDD — Digital supply voltage |
| ピン 10 | VSSD — Digital ground |
| ピン 11 | D0 — Data output bit 0 (LSB) |
| ピン 12 | D1 — Data output bit 1 |
| ピン 13 | D2 — Data output bit 2 |
| ピン 14 | D3 — Data output bit 3 |
| ピン 15 | D4 — Data output bit 4 |
| ピン 16 | D5 — Data output bit 5 |
| ピン 17 | D6 — Data output bit 6 |
| ピン 18 | D7 — Data output bit 7 |
| ピン 19 | D8 — Data output bit 8 |
| ピン 20 | D9 — Data output bit 9 (MSB) |
| ピン 21 | VSSD — Digital ground |
| ピン 22 | VDDD — Digital supply voltage |
| ピン 23 | OE — Output enable |
| ピン 24 | CLKR — Clock return / reference |
| ピン 25 | VSSD — Digital ground |
| ピン 26 | VDDA — Analog supply voltage (5 V) |
| ピン 27 | VSSA — Analog ground |
| ピン 28 | NC — Not connected (per datasheet) |
主な用途
TDA8763AM/3/C5 の用途: 6 件s: DVB / Digital Video IF Sampling, CCD / CIS Image Sensor Digitization, Industrial Process-Control Data Acquisition, Communications IF-Sampling Receiver, Test & Measurement Instrumentation, Medical Imaging Front-End.
DVB / Digital Video IF Sampling
The TDA8763AM/3/C5 is well matched to digitizing the 36 MHz intermediate-frequency output of a DVB tuner chain. Its 30 MSPS sampling rate comfortably exceeds the Nyquist requirement for the 36 MHz IF after digital downconversion, and the 10-bit resolution preserves enough dynamic range for MPEG-2/4 video decoding. The sigma-delta architecture shapes quantization noise out of the baseband video spectrum, which improves demodulator SNR. Place the device close to the tuner IF output with controlled-impedance 50 ohm traces and provide solid AVDD decoupling to limit spurs coupling into the IF signal path.
おすすめ
CCD / CIS Image Sensor Digitization
The TDA8763AM/3/C5 accepts the analog video output stream from a CCD or CIS image-sensor front end at pixel-clock rates up to 30 MHz, converting each pixel sample to a 10-bit digital code. The DC-sampling capability simplifies AC-coupling decisions in the analog path, and the CMOS digital outputs connect directly to an image-processing ASIC or FPGA. The SSOP-28 footprint keeps the analog front-end compact, critical for handheld scanners and digital still cameras. Use a separate analog ground island under the ADC to prevent pixel-clock noise from coupling into the analog input.
おすすめ
Industrial Process-Control Data Acquisition
In industrial data-acquisition systems the TDA8763AM/3/C5 provides 10-bit resolution at 30 MSPS for high-speed analog front-ends such as vibration sensors, sonar return signals, and ultrasonic transducers. The wide analog input bandwidth allows the device to sample IF-derived signals directly, removing the need for external mixers in some designs. The SSOP-28 industrial temperature range (-40 C to +85 C) supports factory-floor deployment. Place robust supply-decoupling networks and isolate the digital outputs from analog input traces to avoid crosstalk into measurement channels.
おすすめ
Communications IF-Sampling Receiver
Software-defined radio and IF-sampling receiver designs use the TDA8763AM/3/C5 to digitize the 10.7 MHz or 21.4 MHz intermediate frequency directly at the output of the final IF stage. At 30 MSPS the converter provides more than 2x oversampling of the IF signal, and the sigma-delta noise-shaping pushes quantization noise outside the channel bandwidth. The single +5 V supply simplifies receiver power-rail design. Connect the digital outputs to an FPGA or DSP for channelization, demodulation, and filtering.
おすすめ
Test & Measurement Instrumentation
Bench-top and modular instrumentation (oscilloscope front-ends, spectrum-analyzer IF strips, digitizer cards) leverage the TDA8763AM/3/C5 to convert analog measurement signals into the digital domain for analysis by an FPGA or DSP. The 30 MSPS sample rate covers many measurement bandwidths up to about 12 MHz, and the 10-bit resolution supports general-purpose waveform capture. The SSOP-28 footprint allows the ADC to be placed directly adjacent to the analog input connector to minimize trace length and parasitic capacitance.
おすすめ
Medical Imaging Front-End
Ultrasound and medical-imaging front-ends use the TDA8763AM/3/C5 to digitize analog return signals at 30 MSPS for beamforming and image reconstruction. The 10-bit resolution provides sufficient grayscale depth for diagnostic imaging, and the single +5 V supply simplifies medical-device safety-isolation design. The sigma-delta architecture reduces anti-alias filter complexity by oversampling the input. Place the ADC close to the transducer preamplifier output, maintain creepage and clearance for patient isolation, and provide separate analog and digital ground planes.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: TDA8763AM/3/C5 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | TDA8763AM/3/C4 | TDA8763AM/4/C5 | TDA8763AM/5/C5 | TDA8763AM/3,118 | TDA8763AM/4,118 |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | SSOP-28 (SOT341-1) | SSOP-28 (SOT341-1) - same | SSOP-28 (SOT341-1) - same | SSOP-28 (SOT341-1) - same | SSOP-28 (SOT341-1) - same | SSOP-28 (SOT341-1) - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit |
| Sampling Rate | 30 MSPS | 30 MSPS | 40 MSPS | 50 MSPS | 30 MSPS | 40 MSPS |
| Architecture | Sigma-Delta | Sigma-Delta | Sigma-Delta | Sigma-Delta | Sigma-Delta | Sigma-Delta |
| Analog Supply | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
主な差別化要因
- Lower power consumption within the same family （vs TDA8763AM/5/C5)
- Wide-margin oversampling at the 36 MHz DVB IF （vs TDA8763AM/4/C5 (40 MSPS))
- Long-established NXP/Philips product specification （vs TDA8763AM/3/C4)
設計ノート
Place a solid analog ground island under the TDA8763AM/3/C5 SSOP-28 footprint and tie all VSSA pins to it with short, wide traces. Run digital ground (VSSD) on a separate island that joins the analog ground at a single point near the ADC. Decouple each VDDA pin with a 100 nF ceramic plus 10 uF bulk capacitor placed within 3 mm of the package, and place a ferrite bead or small resistor in series with the +5 V analog feed to filter switching noise from upstream regulators.
Drive the analog input (VIN) with a low-impedance, AC- or DC-coupled source per the datasheet's input network (typically a resistive divider plus series resistor to set the input common-mode). The CMOS digital outputs D0-D9 should be routed as a tightly-matched parallel bus with a ground reference trace on each side; add 22-47 ohm series damping resistors near the ADC outputs to suppress transmission-line ringing when driving long PCB traces into an FPGA or ASIC.
Do not exceed the maximum analog input voltage or violate the input common-mode range specified in the datasheet - clipping or distortion at the input cannot be corrected in the digital domain. Ensure the CLK input is a clean, low-jitter source; sigma-delta ADCs are particularly vulnerable to clock-jitter-induced noise folding. For new designs, note the part is NXP NRND - plan a migration path to the /4 or /5 family grade or a current-generation NXP ADC.
コンプライアンス情報
RoHS compliant per NXP product page and DigiKey listing. Not AEC-Q100 qualified (consumer/industrial grade). Halogen-free status not explicitly confirmed in the verified web data.
