FPGA & CPLD
제품 (6666)
EP610IPC-25 - 25ns Classic EPLD, 20 I/O, 5V CMOS | Intel/Altera
The Intel (formerly Altera) EP610IPC-25 is a Classic EPLD (Erasable Programmable Logic Device) from the EP610 family, offering a PAL-type architecture implemented in advanced CMOS technology. It provides 25 ns pin-to-pin propagation delay, supports up to 20 inputs and 16 macrocell outputs, and contains 160 product terms for logic integration. The device operates from a single 4.75V to 5.25V supply and is rated for commercial temperature operation from 0°C to 70°C, packaged in a 24-pin plastic DIP (PDIP-24). A Classic EPLD is an early-generation programmable logic device that combines multiple PAL (Programmable Array Logic) and GAL (Generic Array Logic) functions into a single erasable, reprogrammable IC fabricated in CMOS. EPLDs sit in the hierarchy between simple PLDs (PALs/GALs) and modern FPGAs/CPUs - they offer non-volatile, in-system reprogrammable logic that integrates glue logic, state machines, address decoding, and bus interfacing on a single chip. The EP610 family was one of Altera's foundational product lines in the 1980s and remains in service for legacy industrial, military refresh, and long-lifecycle equipment designs. Key features of the EP610IPC-25 include 100% TTL emulation of standard 10K/100K ECL and 74LS logic functions, macrocell-based output architecture with configurable registered or combinatorial outputs, and on-chip erasable CMOS memory for in-system reprogrammability. The device supports multiple package options across the family and is JEDEC-standard pinout compatible within the EP610 series, enabling drop-in speed-grade and temperature-grade substitution. The architecture combines a programmable AND/OR array with dedicated output macrocells, allowing designers to replace dozens of 74LS TTL gates with a single chip. This density advantage, combined with CMOS power consumption (typically under 200 mW active), made the EP610 family a workhorse for industrial control, telecommunications glue logic, and legacy computing systems. The 'IPC-25' suffix denotes the 24-pin plastic DIP package with a 25 ns speed grade. Typical applications include address decoding and bus interfacing in 8086/68000-based embedded systems, glue logic integration in telecommunications equipment, state machine implementation in industrial controllers, and legacy TTL/74LS logic replacement. The wide supply tolerance (4.75V-5.25V) makes it tolerant of unregulated 5V rails commonly found in industrial backplanes. When designing with this device, verify that the 25 ns propagation delay meets your critical timing path requirements - the EP610 family is offered in speed grades from 15 ns to 35 ns. Note that this is an OTP (one-time programmable) windowless plastic package; for prototyping or development use the CERDIP/UV-erasable variants (EP610DC/EP610DM). This page synthesizes distributor pricing, same-family speed-grade alternatives, and practical design notes for the EP610IPC-25 that go beyond the manufacturer datasheet.
EP610JI-30 - 16-Macrocell Classic EPLD, 30ns, CQCC28 Windowed | Altera
The Altera EP610JI-30 is a high-performance, 16-macrocell Classic EPLD (Erasable Programmable Logic Device) from the EP610 family, housed in a 28-pin windowed ceramic JLCC (CQCC28) package and rated for a 30 ns propagation delay. It operates from a single 5 V supply using CMOS PAL-type architecture, with 4 dedicated inputs, 16 I/O lines, and 160 product terms driven by two external clocks, supporting pipelined data rates up to 100 MHz. A Classic EPLD (Erasable Programmable Logic Device) is a UV-erasable member of the programmable logic family, sitting between simple PAL/GAL devices and modern CPLDs/FPGAs in the design complexity hierarchy (PAL/GAL -> Classic EPLD -> MAX CPLD -> FPGA). The windowed ceramic package contains a quartz window that allows the device's internal EPROM configuration memory to be erased with ultraviolet light, enabling hundreds of reprogramming cycles during prototyping and design iteration. The 16-macrocell Classic architecture is sum-of-products based, with a global bus interconnecting the AND/OR arrays to a programmable output macrocell register bank. Key features of the EP610JI-30 include the 32 ns propagation delay window (often marketed as 30 ns grade per the speed suffix), 100 MHz pipeline throughput, JTAG-free boundary-scan-free classic programming via the Altera programming algorithm, and 5 V CMOS I/O. The device supports bidirectional I/O, programmable output enables, and registers on every macrocell, making it a flexible glue-logic replacement for discrete TTL/CMOS gate arrays in legacy designs. Two clock inputs feed the device's internal register clock network. The EP610 architecture uses an EPROM-based sum-of-products structure with a programmable interconnect array feeding 16 output macrocells. Each macrocell contains a programmable flip-flop, output polarity selection, and tri-state control. This architecture gives deterministic tpd that does not depend on routing congestion, a major advantage over early FPGA architectures of the same era, and the part supports synchronous and asynchronous clocking schemes with predictable pin-to-pin timing. Typical applications for the EP610JI-30 include legacy bus-interface glue logic, address decoding for M68000/i8086 systems, state-machine replacement in industrial controllers, TTL/CMOS gate-array consolidation, and prototyping of glue logic where modern FPGAs are not required. The windowed package is specifically chosen for engineering development and low-volume production where in-house UV erasure and reprogramming provide the lowest total cost. When designing with this part, note that the EP610 requires an Altera-compatible programmer (e.g., Altera Logic Programmer or third-party equivalents). Decoupling must use a 0.1 microfarad ceramic capacitor per VCC pin placed within 5 mm of the package. Inputs float when not driven; tie unused inputs to VCC or GND through a 10 kohm resistor to avoid CMOS shoot-through current. This page synthesizes distributor stock status, JLCC28 package diagrams, and pin-compatible Classic EPLD alternatives not consolidated in the original Altera datasheet, helping sourcing engineers extend the lifecycle of legacy Classic EPLD designs.
EP610LC-15 - 16-Macrocell Classic EPLD, 15ns PLCC-28 | Altera
The Altera EP610LC-15 is a high-performance, 16-macrocell Classic EPLD (Erasable Programmable Logic Device) housed in a 28-pin PLCC package with a 15 ns propagation delay and pipelined data rates up to 100 MHz. This CMOS-era Erasable Programmable Logic Device (EPLD) integrates 300 usable gates and 16 macrocells into a deterministic, non-volatile logic fabric, making it a foundational part for glue-logic integration in 5 V industrial systems. The device supports in-system UV-erase (windowed versions) and one-time-programmable (OTP) configurations, with -15 speed grade delivering 15 ns pin-to-pin delay. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that pre-dates modern FPGAs and CPLDs. In the taxonomy, an EPLD sits between a PAL (Programmable Array Logic) and a modern CPLD/FPGA: like a PAL, it is non-volatile and instant-on, but like a modern CPLD it contains multiple macrocells with sum-of-products logic and a fixed interconnect. The Classic EPLD family from Altera was widely adopted in the 1980s and 1990s as a higher-density, faster alternative to discrete PAL/GAL devices for state machines, address decoding, and bus-interface logic. Key features of the EP610LC-15 include 16 macrocells with 16 dedicated flip-flops, propagation delays of 15 ns, fmax of 83.3 MHz counter frequency (and pipelined throughput up to 100 MHz), 24 input pins, and 16 output pins in the J-lead PLCC-28 footprint. The device operates from a single 5 V supply and is fabricated in CMOS technology, providing low static power consumption compared to bipolar PALs of the same era. Architecturally, the EP610LC-15 uses a sum-of-products (AND-OR) plane feeding configurable macrocell flip-flops, with a global interconnect that guarantees deterministic, predictable timing - critical for synchronous state-machine design. This deterministic timing, plus non-volatile configuration, makes Classic EPLDs preferred over early FPGAs in safety- and timing-critical industrial applications. The device is currently maintained by Rochester Electronics, LLC as an authorized Altera licensee for long-lifecycle programs. Typical applications include bus-interface glue logic, address decoding and chip-select generation, state-machine controllers, and replacement of discrete 74LS/74F TTL logic in 5 V systems. The wide operating voltage (single 5 V) and PLCC footprint also made it a common choice in industrial control, telecommunications backplane, and military/aerospace programs where long-term supply continuity is mandatory. When designing with this device, note that programming requires a compatible EPROM/UV eraser and programmer (e.g., Data I/O or BP Microsystems), and design entry is typically performed with classic Altera MAX+PLUS II or equivalent tools. Designers should also verify available package alternatives (windowed ceramic vs. plastic OTP) before committing to a long-lifecycle design. This page synthesizes Rochester Electronics distributor pricing, same-family Altera Classic drop-in alternatives, and practical design notes for long-lifecycle EPLD programs - information not consolidated in any single manufacturer datasheet.
EP610LC-25 - 16-Macrocell Classic EPLD, 25ns, PLCC-28 | Intel
The Intel EP610LC-25 is a 16-macrocell CMOS Classic EPLD (Erasable Programmable Logic Device) with a 25 ns propagation delay, housed in a 28-pin PLCC package. It is part of Altera's original Classic EPLD family, designed for high-performance glue-logic replacement of discrete TTL and PAL/GAL devices in 5V systems. The device delivers pipelined data rates of up to 100 MHz and offers 16 macrocells organized into four Logic Array Blocks (LABs), each containing four macrocells. A Classic EPLD is a type of programmable logic device (PLD) that combines the low cost and simplicity of PAL/GAL architectures with the flexibility and density of early FPGA-like logic. In the broader taxonomy, the EP610LC-25 sits within: programmable logic device -> erasable PLD -> CMOS EPLD -> Classic EPLD family. The EP610 family was introduced in the late 1980s as one of the first UV-erasable CMOS PLDs suitable for high-speed state machine and bus-interface applications. Key features include 16 macrocells, 25 ns maximum pin-to-pin propagation delay (tPD), a 100 MHz maximum toggle frequency, and a 5V ±5% supply requirement. The device is in-system or window-erasable (UV forcerasable ceramic windowed variants) and supports industry-standard JEDEC file formats for programming. Per the Altera Classic Device Family datasheet, the EP610 provides bidirectional I/O, programmable output enable, and configurable flip-flop polarity in every macrocell. The architecture uses an AND/OR PLA-style logic array with a fixed OR plane feeding programmable flip-flop macrocells, providing predictable timing with no routing delay variance. Each macrocell contains a flip-flop, output polarity control, and a tri-state output buffer, enabling implementation of both combinatorial and registered logic with deterministic timing. Typical applications include bus-interface glue logic, state-machine controllers, address decoders, and 5V legacy system replacements. The 28-pin PLCC footprint is socket-compatible with standard 28-pin PLCC sockets, enabling easy drop-in replacement of older PAL/GAL devices. When designing with this part, designers should ensure 5V ±5% supply tolerance and provide adequate decoupling (100 nF ceramic near VCC). For new designs, modern CPLDs such as the Altera MAX II family or Lattice ispMACH 4000 series offer substantially higher logic density, lower power, and in-system programmability. This page synthesizes distributor availability, pin-compatible alternatives from the same Classic EPLD family, and practical design notes not found in the manufacturer datasheet.
EP610LC-30 - 16-Macrocell Classic EPLD, 30ns, 5V | Altera / Intel
The Altera (Intel) EP610LC-30 is a 16-macrocell Classic Erasable Programmable Logic Device (EPLD) from the EP610 family, offered in a 24-pin ceramic or plastic DIP/Cerdip package with a 30 ns pin-to-pin propagation delay and 5 V CMOS supply operation. It is built on an advanced CMOS EPROM process that combines high-speed logic integration with low static power consumption and supports pipelined data rates of up to 100 MHz for high-performance glue-logic replacement. A Classic EPLD is a non-volatile programmable logic device sitting in the hierarchy of simple PLDs -> EPLD/CPLD -> programmable logic -> semiconductor. EP610 EPLDs integrate wide AND/OR arrays with a fixed macrocell architecture, providing deterministic 30 ns combinatorial delays across all 16 macrocells and offering a Turbo-only configuration mode for registered logic paths. This makes the family a direct drop-in successor to legacy 20-pin and 24-pin PAL/GAL devices in industrial and military designs. Key features include 16 macrocells, 5 V single-supply operation (VCC = 4.75 V to 5.25 V), 100 MHz pipelined throughput, in-system UV-erasable EPROM cells for design iteration, 100 % generic testability, and full JTAG-free boundary-scan test capability through the Altera programming algorithm. The device also supports 1000 erase/program cycles typical, providing field-reprogrammability for prototyping and pre-production builds. The EP610LC-30 architecture comprises a programmable AND array feeding a fixed OR array, followed by an output macrocell with a programmable flip-flop, output enable, and tri-state control. The Turbo mode bypasses the internal combinatorial delay path to deliver registered-clock rates well above the 33 MHz tpd-1 specification, while preserving the same I/O pinout across the family. Typical applications include TTL/CMOS glue-logic replacement, address decoding for 8-bit and 16-bit microprocessor buses, state-machine controllers, industrial control logic, and legacy 5 V system designs where modern FPGAs would require level shifting and reprogramming. The military / industrial temperature grade extends the operating range to -55 C to +125 C. When designing with the EP610LC-30, ensure that VCC decoupling (0.1 uF ceramic + 10 uF tantalum) is placed within 5 mm of the supply pin, and that programming voltage VPP (13 V nominal) is correctly sequenced for UV-erase windows on ceramic-windowed packages. Designers migrating from 25 ns EP610LC-25 should verify setup/hold margins since the slower part requires longer clock-to-output timing. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, helping sourcing engineers validate second-source decisions for legacy 5 V EPLD sockets.
EP610LC-35 - 16-Macrocell Classic EPLD, 37ns, 5V, PLCC-35 | Altera
The Altera EP610LC-35 is a Classic-series Erasable Programmable Logic Device (EPLD) from the EP610 family, delivering 16 macrocells, 300 usable gates, and a 37 ns propagation delay in a 28-pin plastic J-lead chip carrier (PLCC) package. It operates from a single 5 V supply and is fabricated in CMOS technology for low power consumption. A Classic EPLD is a non-volatile programmable logic device that combines the integration of a PLD with erasable CMOS architecture, sitting in the hierarchy between discrete 22V10-style SPLDs and modern SRAM-based FPGAs. The EP610 family targets glue-logic replacement, state-machine implementation, and decoder/encoder functions in 5 V systems where a small number of logic functions must be implemented in a single package. Key features include 24 dedicated input pins, 16 output macrocells, 4 combinatorial feedback paths per macrocell, programmable I/O architecture, and a synchronous prescaler for flexible clock division. The Classic family supports 100% factory-tested AC and DC specifications with on-board logic-test circuitry that enables standard production-flow verification. Macrocells share a sum term and product term, allowing wide-input AND/OR functions to be combined with registered outputs. The EP610 uses CMOS EEPROM-based configuration cells backed by UV-erasable windowed ceramic variants (EP610I/J) and one-time-programmable plastic variants (EP610L/D). Architecture-wise, every macrocell contains a flip-flop, an output enable, and feedback into the AND-array, supporting both registered and combinatorial outputs from the same physical pin. The 37 ns tpd speed grade (-35) is the slowest of the EP610 family and trades timing margin for slightly lower dynamic current draw at lower toggle rates. Typical applications include 5 V bus decoding, address mapping for microcontroller and 8-bit/16-bit processor systems, state-machine controllers, glue-logic consolidation in industrial control boards, and replacement of legacy 22V10 PAL/GAL devices. The wide supply tolerance makes it usable in 5 V-only industrial backplanes where modern 3.3 V-only CPLDs are not pin-compatible. When designing with this part, note that the -35 speed grade is the slowest EP610 variant; verify timing margins carefully when porting -25 or -15 designs. Programming is performed via the Altera MAX+PLUS II development system and a hardware programmer; source files are still maintained in the Altera Classic Device Family support archive. This page synthesizes distributor pricing, Rochester Electronics stock status, same-family speed-grade and package alternatives, and practical design notes that go beyond the marketing blurb in the original datasheet.
EP610LC15 - 16-Macrocell Classic EPLD, 15ns, 5V, PLCC-28 | Rochester
The Rochester Electronics EP610LC15 is a 16-macrocell Classic EPLD (Erasable Programmable Logic Device) with a 15 ns propagation delay, supplied in a 28-pin PLCC package and fabricated on a 5V CMOS process with UV-erasable windowed ceramic package option. The Classic family provides glue-logic integration at pipelined data rates of up to 100 MHz and is fully compatible with the original Altera Classic EPLD architecture that defined the segment in the late 1980s. A CPLD/EPLD is a non-volatile programmable logic device that combines multiple PAL-style macrocell arrays on a single die, allowing designers to replace dozens of 74-series SSI/MSI glue-logic packages with a single erasable part. EPLDs sit in the broader taxonomy programmable logic device (PLD) -> EPLD/CPLD -> CMOS programmable logic -> digital semiconductor, and historically predate modern flash-based CPLDs and SRAM-based FPGAs. The Classic architecture uses a sum-of-products AND-OR array followed by an output macrocell with selectable flip-flop polarity, making it well suited for state machines, address decoding, and bus interface logic. Key features of the EP610LC15 include 16 macrocells, 10 dedicated inputs, 16 I/O pins forming a 24-pin logic array, a 15 ns pin-to-pin propagation delay (tPD), a 83.3 MHz maximum toggle frequency, and a single 5V (±10%) supply with TTL-compatible I/O. The device is in-system programmable via the Altera-standard 4-pin JTAG-style serial interface and supports security-bit protection to lock the programmed pattern. The EP610 architecture uses an EPROM-based AND array driving a fixed OR array, with each macrocell containing a programmable flip-flop, output enable, and feedback path. The 5V CMOS process yields zero standby current on disabled outputs and typical quiescent current in the low milliamp range, while the ceramic-windowed package allows pattern erasure under UV light for prototyping and design iteration. Typical applications include bus decoding for 8086/68000 microprocessor systems, address decoding for memory and peripheral mapping, state-machine implementation in industrial controllers, and TTL-to-CMOS level-interface bridging in legacy 5V designs. The 83.3 MHz fMAX also supports small pipelined datapath functions such as counter chains, frequency dividers, and shift registers. When designing with the EP610LC15, observe that the LC suffix denotes the commercial 0°C to +70°C operating range and the 15 ns speed grade; the -15 speed bin is the slowest of the EP610 family and should be selected only when timing slack allows. Programming requires a hardware programmer supporting the Classic EPLD algorithm (e.g., Altera PL-ASAP or Data I/O). Lead-finish options are matte-tin over nickel (lead-free) per modern Rochester Electronics re-creation, RoHS compliant. This page consolidates Rochester Electronics and Altera datasheet specs, cross-brand 5V-CPLD drop-in candidates, and design notes for legacy 5V glue-logic replacement that distributor listings do not present in one place.
EP610LI-15 - 16-Macrocell CMOS EPLD, 15ns tPD | Altera (Rochester)
The Altera EP610LI-15 is a 16-macrocell ultraviolet-erasable CMOS Erasable Programmable Logic Device (EPLD) from the Classic EP610 family, supplied as a long-retail product by Rochester Electronics. It offers a pin-to-pin propagation delay (tPD) of 15 ns, a counter frequency fCNT of 83.3 MHz, and is housed in a 24-pin ceramic side-brazed DIP package (windowed, for UV erasure). The "LI" suffix denotes the commercial temperature grade (0C to +70C) and low-power CMOS process variant, while "-15" specifies the 15 ns speed grade. What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that combines the non-volatility and pin-out predictability of PAL/GAL devices with the higher integration of early PLDs. In the system hierarchy, an EPLD sits between simple SPLDs (PAL/GAL) and CPLDs/FPGAs: it provides AND/OR array logic with user-programmable macrocells but offers a fixed architecture (no SRAM-based interconnect), making timing deterministic and easy to simulate. The EP610 family is the second-generation Classic EPLD line introduced after the EPROM-based EP1200 series, using a CMOS EPROM cell instead of a fuse, which made it re-programmable in-system via UV erasure. Key features of the EP610LI-15 include 16 macrcells delivering up to 48 product terms per macrocell in sum-of-products form, 100% TTL-level compatibility on inputs and outputs, and a 5 V single-supply operation. Inputs are CMOS/TTL-compatible and outputs are 3-state, allowing bus-oriented designs. The device is in-system programmable via standard EPROM programmers after UV exposure through the quartz window. Architecturally, the EP610LI-15 uses a programmable AND-OR-NOT array feeding 16 output macrocells, each containing a flip-flop and output enable. The fixed interconnect eliminates the routing-variation headaches of FPGAs and gives predictable tCO and tSU timing - useful for legacy glue-logic replacement in industrial controllers, telecom backplanes, and military refresh programs. Today the part is supported as a long-term sustainment product by Rochester Electronics, the authorized Altera/Intel legacy distributor, with 2917 units in stock per the LCSC listing as of 2026-09-10. Typical applications include address decoding in 8086/68K microprocessor systems, peripheral glue logic in VMEbus designs, state-machine controllers for industrial automation, and TTL-to-CMOS logic replacement in legacy telecom equipment. Its deterministic timing also makes it suitable for instrumentation front-ends where predictable propagation delay matters. When designing with this device, mind the 15 ns tPD budget: at 40 MHz bus rates the device is borderline, so allow one wait state if driving a fast microprocessor. The DIP-24 ceramic package requires a socket if UV erasure is planned, since desoldering a ceramic DIP repeatedly will damage pads. This page synthesizes distributor stock, lifecycle status, and drop-in same-family alternatives (EP610LI-12, EP610LC-15) not found in a single source on the manufacturer datasheet.
EP610LI-20 - Classic 16-Macrocell EPLD, 20ns | Rochester/Altera
The Rochester Electronics (originally Altera) EP610LI-20 is a Classic-series Erasable Programmable Logic Device (EPLD) featuring 16 macrocells, a 20 ns pin-to-pin propagation delay, and operation from a single 4.5 V to 5.5 V supply. Housed in a 28-pin PLCC (PQCC28) package, it is supplied today through Rochester Electronics' authorized aftermarket channel as a long-life sustaining solution for legacy Altera EP610 designs. What is a Classic EPLD? An Erasable Programmable Logic Device is a UV-erasable, electrically programmable logic IC that preceded modern CPLDs and FPGAs. Conceptually, an EPLD sits in the programmable logic hierarchy as follows: programmable logic device (PLD) -> EPLD (UV-erasable) -> CPLD (modern non-volatile equivalent) -> FPGA (largest, SRAM-based). Each Classic EPLD macrocell combines a programmable AND-OR array with a flip-flop, allowing replacement of multiple SSI/MSI glue-logic packages with a single reprogrammable device. Key features of the EP610LI-20 include 16 macrocells, 24 dedicated input pins, 20 I/O pins, a maximum toggle frequency of 100 MHz, 20 ns tPD (pin-to-pin) at worst-case commercial conditions, and CMOS technology with low standby current. The 'LI' suffix denotes the industrial temperature range (-40C to +85C) and 20 ns speed grade, while the 'L' package suffix indicates a PLCC (Plastic Leaded Chip Carrier) JEDEC outline. The EP610LI-20 implements a sum-of-products AND-OR array per macrocell with an output flip-flop and a programmable output enable. Architecturally, it offers predictable, deterministic timing suitable for replacing PAL/GAL devices with higher macrocell density. The device is programmed using a standard Altera programming algorithm via dedicated programming hardware. Typical applications include industrial control glue logic, address decoding for legacy microprocessor boards (Intel 8086/8088, Motorola 68k), bus-interface adaptation, state-machine replacement, and prototyping of discrete SSI/MSI logic functions. The PLCC-28 socket-compatible footprint also enables direct substitution onto existing Altera EP610, EP610I, and EP910 boards when pin-compatible speed grades are required. When designing with the EP610LI-20, ensure the supply rail is decoupled with 0.1 uF ceramic capacitors close to each VCC pin and that unused inputs are tied to VCC or GND to avoid oscillation. Because the part is UV-erasable, designs requiring field re-programmability must include a windowed (ceramic) package variant or migrate to a modern MAX-series CPLD for in-system programmability. This page synthesizes distributor pricing, same-brand Altera/Rochester EP610 family drop-in alternatives, and practical design notes not collated in the original datasheet, helping engineers sourcing legacy EPLDs extend the lifecycle of installed equipment without PCB rework.
EP610LI-25 - 16-Macrocell Classic EPLD, 25ns, CMOS | Altera / Rochester Electronics
The Altera (Rochester Electronics) EP610LI-25 is a 16-macrocell Classic EPLD from the EP610 family, providing 300 usable gates with 25 ns maximum propagation delay in a CMOS, low-power 'L' speed-grade variant. This Classic-family Erasable Programmable Logic Device (EPLD) integrates AND/OR logic arrays with programmable macrocells, offering pipelined data rates up to 100 MHz and pin-compatible migration within the EP610 family. The part is supplied in a ceramic/through-hole or windowed ceramic DIP package designated 'I' for industrial temperature grade. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC (PLD) that combines multiple PAL-like macrocells on a single CMOS die, erasable via ultraviolet light through a quartz window on windowed packages. Classic EPLDs occupy the architectural middle ground between simple PALs/GALs and modern high-density FPGAs or CPLDs: they offer deterministic combinatorial and registered logic, predictable pin-to-pin timing, and simple development flows based on Altera's legacy MAX+PLUS II / Classic compiler toolchain. In a system hierarchy, EPLDs sit under CPLDs and FPGAs but above discrete 74-series glue logic for designs needing a few hundred gates of custom decode, state-machine, or bus-interface logic. Key features include 16 macrocells, 300 usable gates, 25 ns tPD, 100 MHz pipelined fMAX, 4 dedicated inputs plus 16 I/O pins, and programmable output macrocell polarity. The device offers three-state output control on every I/O pin, a synchronous preset/reset structure shared across the macrocell array, and low CMOS standby current typical of the 'L' power variant. JTAG/boundary-scan test is not present on this Classic part - test access is via the standard functional pins and the dedicated programming algorithm. From an architectural standpoint, the EP610 is a sum-of-products AND-OR array feeding a global interconnect that drives 16 output macrocells. Each macrocell contains a flip-flop, output polarity bit, and three-state buffer that can be individually enabled. This structure delivers predictable, deterministic timing that does not require place-and-route iteration, making EP610 designs reproducible across production lots. Typical applications include legacy glue-logic replacement on industrial and military backplanes, address decoding for 8- and 16-bit microprocessor systems (8086, 68000, Z80), bus arbitration and interrupt controllers, state-machine controllers, and small peripheral interfaces where modern CPLD/FPGA density is unnecessary. The 'I' temperature grade and ceramic package also make it suitable for extended-temperature and Mil-spec system designs still in active production. When designing with EP610LI-25, use Altera MAX+PLUS II or the Classic compiler with a supported programmer, and respect the 25 ns tPD budget when cascading logic across multiple macrocells. For new designs, prefer the EP610LI-20 or EP610LI-15 speed grades if timing margin is tight; the EP610 family shares pinout across all speed grades, simplifying speed up/down swap on existing boards. This page synthesizes distributor pricing from Rochester Electronics and authorized partners, lists same-family drop-in pin-compatible alternatives from the EP610 family, and surfaces practical programming and design notes not consolidated in the original Altera datasheet.
EP610LI-30 - 16-Macrocell Classic EPLD, 30ns | Rochester
The Rochester Electronics EP610LI-30 is a high-performance, 16-macrocell Classic Erasable Programmable Logic Device (EPLD) offering pipelined data rates of up to 100 MHz and a 30 ns pin-to-pin propagation delay, supplied in a 24-pin ceramic DIP package. Originally designed by Altera and now manufactured and supported by Rochester Electronics, this member of the Classic EPLD family integrates multiple 24V18 macrocell PAL-like AND/OR arrays into a single CMOS device, replacing 4 to 8 discrete SSI/MSI TTL or CMOS logic packages with one programmable part. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC that combines the architectural density of a PLD with the erasability of an EPROM. Within the broader semiconductor taxonomy, EPLDs sit between simple SPLDs/CPLDs and large FPGAs: they offer deterministic timing, low static power consumption, and zero in-system configuration time because the logic is realized in silicon at manufacture-time via fuse/anti-fuse links rather than SRAM lookup tables. The Classic EPLD family historically targeted glue-logic replacement, address decoding, state-machine encoding, and bus-interface adaptation in industrial, telecommunications, and legacy computing designs. Key features include 16 sum-of-products macrocells with user-configurable output polarity, a 5 V CMOS core with TTL-compatible I/O, an internal 24V16 AND array, and a built-in test mode for verification. The device is fabricated in UV-erasable CMOS technology and is windowed ceramic DIP-packaged for military and aerospace programs that require proven, long-life-cycle silicon. The EP610LI-30 uses a MAX-type macrocell architecture with a configurable D/T/J-K flip-flop per cell, a global clear and a product-term clock network, and a synchronous preset that simplifies state-machine design. The pipelined register path allows internal fMAX up to 100 MHz, while combinational paths at 30 ns make the part well-suited to legacy system-clock domains of 25-33 MHz. Typical applications include legacy peripheral adapter cards, industrial motor-control glue logic, MIL-STD-1553 bus interface decoding, telecom backplane address decoding, and avionics retrofit programs. The device is especially useful when modern FPGAs are overkill or where a non-volatile, instantly-on logic element is required. When designing with this part, note that the 'LI' suffix denotes a windowed ceramic DIP for MIL/Aero temperature ranges (-55C to +125C), so erase/programming requires a UV eraser and a Classic-series programmer (e.g., Altera PLDS-JAM). Designers migrating to surface-mount should consider the equivalent PLCC-package variant. This page synthesizes Rochester stock data, same-family drop-in alternatives, and Classic EPLD design notes not found in the legacy Altera datasheet, helping engineers source obsolete EPLD silicon for long-life programs.
EP610LI-35 - 16-Macrocell Classic EPLD, 35ns, PLCC-28 | Altera
The Altera EP610LI-35 is a high-performance 16-macrocell Classic EPLD (Erasable Programmable Logic Device) from the EP610 family, delivering pipelined data rates of up to 100 MHz in a 28-pin PLCC package. Operating from a single 5 V supply, the device integrates 300 usable gates and 16 macrocells interconnected via a programmable AND-OR array, with 20 total inputs and 16 I/O lines. The 'LI' suffix denotes a windowed ceramic package suitable for military temperature range operation, while the '35' speed grade specifies a 35 ns propagation delay. A Classic EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that uses EPROM, EEPROM, or Flash cells to store the configuration. CPLDs/EPLDs belong to the broader hierarchy of programmable logic devices (PLDs), which sit between discrete logic ICs and full FPGAs in density and complexity. The Classic family implements a PAL-style AND-OR architecture with macrocells containing flip-flops, making it ideal for glue logic, state machines, and bus interfacing in 5 V systems. Key features of the EP610LI-35 include PAL-type architecture with 16 macrocells, 160 product terms for wide sum-of-products logic, 4 dedicated inputs plus 2 external clock inputs, and CMOS technology for low power consumption. The device provides in-system programmable logic with high noise immunity typical of CMOS designs, supporting synchronous designs through dedicated clock networks and asynchronous designs through programmable flip-flops. The EP610 architecture uses a programmable interconnect scheme with each macrocell containing a configurable flip-flop with preset/reset capability. Logic is implemented as sum-of-products terms that feed the 16 macrocell flip-flops, which can be configured as D, T, JK, or SR types. This architecture is well suited to decoder, encoder, and state-machine implementations where deterministic timing is critical. Typical applications include bus interface glue logic, address decoding, state machines, and peripheral control in legacy 5 V systems. The wide 5 V tolerance makes it suitable for industrial control and replacement of discrete TTL/CMOS logic, particularly in long-lifecycle equipment where modern FPGAs are unsuitable. The windowed ceramic package enables reprogrammability for prototype development and field updates. When designing with the EP610LI-35, ensure that all unused I/O pins are properly terminated to avoid floating-input issues in CMOS designs. The 35 ns propagation delay must be analyzed against the target system's timing budget, with attention to the worst-case delay paths through multiple logic levels.
EP610PC-15 - 16-Macrocell Classic EPLD, 15ns PDIP-24 | Altera
The Altera (now Intel) EP610PC-15 is a Classic EPLD (Erasable Programmable Logic Device) from the original Altera Classic family, delivering 300 usable gates, 16 macrocells, and a 15ns pin-to-pin logic delay in a 24-pin plastic DIP (PDIP) through-hole package. It operates from a single 5V supply and supports pipelined data rates of up to 100 MHz, making it the slowest-speed grade in the EP610 Classic EPLD lineup but still suitable for many glue-logic and bus-interface tasks. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC that combines the architectural simplicity of PAL/GAL devices with higher gate density and on-chip macrocell registers. Within the broader taxonomy, the EP610 belongs to the chain: EPLD -> CPLD -> Programmable Logic Device (PLD) -> Logic IC -> Integrated Circuit. Classic EPLDs are CMOS UV-erasable parts historically used to replace multiple discrete PAL/GAL chips with a single, in-system reconfigurable device, sitting upstream of the FPGA family in the programmable-logic evolution. Key features of the EP610PC-15 include 100% TTL emulation, on-board logic test circuitry for AC/DC verification during production flow, integrated macrocell flip-flops, and a choice of speed grades (-15, -20, -25, -30, -35) with the -15 being the slowest variant. The Classic family supports 300 to 900 usable gates, but the EP610 specifically targets the 16-macrocell / 300-gate entry point for low-density glue logic. It is a PAL-type architecture with CMOS technology and a 17 ns tPD (per Datasheets360 listing). The device architecture is based on a sum-of-products PLA-style AND/OR array feeding 16 macrocells, each with a programmable flip-flop and I/O control. This makes the EP610PC-15 well-suited to state-machine, address-decoding, and bus-arbitration functions where non-volatility, deterministic timing, and a simple development toolchain (MAX+PLUS II) are valued. Typical applications include address decoding in 8086/68k/MIPS-based systems, glue logic between microprocessors and peripherals, bus arbitration, state-machine controllers, and legacy industrial control replacement where original Altera Classic parts must be form-fit-function substitutes. Because the EP610 is in production through Rochester Electronics as a long-life sustaining product, it continues to be specified for EOL (end-of-life) boards and long-lifecycle aerospace/defense programs. When designing with this device, note that the 15ns grade has the slowest tPD in the family - if your timing budget is tight, choose -20, -25, -30, or -35 instead. Verify the supply voltage (5V only) and the package footprint (24-pin PDIP, 0.3 inch row spacing) match the legacy PCB layout before substitution. This page synthesizes Rochester Electronics distributor pricing, same-family drop-in alternatives, and design notes not found in the original Altera datasheet, providing practical sourcing intelligence for engineers maintaining legacy EPLD designs.
EP610PC-20 - Classic EPLD, 16 Macrocells, 100 MHz | Altera
The Altera (Rochester Electronics) EP610PC-20 is a Classic-family Erasable Programmable Logic Device (EPLD) with 16 macrocells, 300 usable gates, and pipelined data rates of up to 100 MHz, housed in a 24-pin PDIP package. The -20 speed grade denotes a 20 ns pin-to-pin propagation delay (tPD), suitable for high-performance glue-logic and state-machine replacement in legacy 5 V systems. According to Rochester Electronics' datasheet excerpt, the device is fabricated in CMOS EPROM technology, supports in-system UV erasure via a windowed package option, and is pin-compatible with the broader EP610 family. A Classic EPLD is a type of programmable logic device that combines the non-volatility and instant-on behavior of EPROM with the flexibility of combinatorial and sequential logic implementation. In the system hierarchy, an EPLD sits between simple PLDs (PAL/GAL) and modern CPLDs/FPGAs, providing predictable timing, deterministic propagation delay, and a small macrocell count optimized for fast logic integration. The EP610 was Altera's second-generation Classic EPLD, designed for high-speed decoder, counter, and bus-interface applications where bipolar PALs lacked speed or density. Key features of the EP610PC-20 include 16 macrocells, 24 dedicated input pins, 16 flip-flops with individual clear/preset control, programmable output polarity, and a 5 V ±10% single-supply operation. The device offers 100 MHz registered operation, 20 ns tPD (commercial grade), and a maximum I/O count consistent with the 24-pin PDIP footprint. The architecture is a sum-of-products array feeding 16 macrocells, with each macrocell containing a programmable flip-flop and output enable logic, allowing implementation of either combinatorial or registered logic functions. Architecturally, the EP610 uses a unified AND/OR array with a fixed internal interconnect, eliminating the routing variability of FPGAs. The CMOS EPROM process provides zero standby power and full TTL compatibility, while the deterministic tPD enables accurate timing analysis without static timing closure tools. Compared to bipolar 20 ns PALs, the EP610PC-20 adds programmability of registered outputs and eliminates the need for separate PAL/flip-flop pairs on a board. Typical applications include bus decoders and address-mapping logic in 8086/68000-era microprocessor systems, high-speed glue logic between ASICs and standard peripherals, replacement of multiple 20 ns PALs with a single device, DMA state machines, interrupt controllers, and legacy industrial control designs. The 100 MHz pipelined throughput also makes the device useful for frequency-division and clock-distribution networks. When designing with the EP610PC-20, ensure that the 5 V supply is within ±10% tolerance, place a 0.1 µF decoupling capacitor near each VCC pin, and confirm that the device programmer supports the Classic EPLD algorithm (e.g., Data I/O, BP-1200, or equivalent). For production, use the one-time-programmable (OTP) windowless variant if UV erasure is not required, and program the security bit to prevent pattern readback. This page synthesizes distributor pricing from Rochester Electronics and authorized resellers, same-family drop-in alternatives (EP610PC-15, EP610LC-25, EP610DC-25) from the Site MPN list, and practical design notes not found in the original manufacturer datasheet.
EP610PC-20T - 16-Macrocell Classic EPLD, 20ns, PDIP-24 | Intel
The Intel (formerly Altera) EP610PC-20T is a 16-macrocell Classic EPLD (Erasable Programmable Logic Device) with 300 usable gates, a 20 ns pin-to-pin propagation delay, and a 62.5 MHz pipelined data rate, housed in a 24-pin plastic DIP (PDIP) through-hole package. It is a UV-erasable, CMOS Classic-series EPLD designed for glue-logic and state-machine replacement in legacy 5V systems. A CPLD/EPLD is a non-volatile programmable logic device that retains its configuration when power is removed, sitting in the broader hierarchy of programmable logic devices (PLD) -> CPLD -> EPLD -> programmable logic IC. Classic EPLDs predate modern flash-based CPLDs and are widely used for board-level integration of random logic, address decoding, bus arbitration, and peripheral control in industrial, telecom, and military systems where 5 V tolerance and proven long-term reliability are required. Key features of the EP610PC-20T include 16 macrocells, 16 dedicated inputs plus pin feedback, 4 product-term OR arrays, a 5 V VCC supply, a 20 ns tPD commercial-grade speed grade, and on-board logic test circuitry that allows verification of function and AC specifications during standard production flow. The 'PC' suffix denotes the PDIP package, '20' denotes the 20 ns speed grade, and the 'T' indicates tape-and-reel packaging. The device is programmed using the MAX+PLUS II development system and supports the Classic-series JTAG-compatible programming interface. The EP610PC-20T is built on a CMOS EEPROM/EPROM-based architecture with on-chip charge pumps for in-system programming, programmable interconnect, and product-term logic arrays per macrocell. Each macrocell contains a programmable register, feedback path, and output enable control. Designers can synthesize combinational or registered logic up to 300 gates equivalent, replacing dozens of discrete 74-series TTL/CMOS parts. Typical applications include 5 V address decoding, glue logic for ISA/VME bus systems, state-machine replacement in industrial controllers, microcontroller I/O and peripheral expansion, and legacy telecom line-card interface logic. The through-hole PDIP-24 package is well suited to through-hole PCB assembly, prototype boards, and MIL-spec or ruggedized designs. When designing with the EP610PC-20T, remember that Classic EPLDs use the legacy MAX+PLUS II toolchain; modern Quartus support is limited. Decoupling 0.1 uF ceramic caps must be placed on every VCC/GND pair, unused inputs must be tied to VCC through a 10 kohm resistor, and the device must be erased under UV light before reprogramming. This page synthesizes distributor pricing, drop-in same-brand speed-grade alternatives, pinout diagrams, and practical design notes that are not aggregated on the manufacturer datasheet or single distributor listings, giving engineers a single decision-grade reference.
EP610PC-25 - 16-Macrocell Classic EPLD, 25ns PDIP-24 | Altera
The Altera (Intel) EP610PC-25 is a Classic EPLD (Erasable Programmable Logic Device) from the EP610 family, delivering 16 macrocells, 300 usable gates, and 25 ns pin-to-pin propagation delay in a 24-pin PDIP (0.3 inch) through-hole package. It is a CMOS PAL-type OTP (one-time programmable) PLD with pipelined data rates up to 100 MHz and operates from a single 5 V supply. What is a Classic EPLD? An EPLD (Erasable Programmable Logic Device) is a type of Programmable Logic Device (PLD) that combines the non-volatility and simple programming model of a PAL (Programmable Array Logic) with the higher macrocell density of early complex PLDs. Classic EPLDs sit in the hierarchy between simple PAL/GAL devices and modern CPLDs/FPGAs, providing AND/OR plane logic with user-configurable macrocell flip-flops. EP610-class devices were commonly used to replace discrete 74LS glue logic and SSI/MSI PALs in 5 V industrial and computer-peripheral designs. Key features include 16 macrocells (organized as four 16x8 PAL-like blocks of four macrocells each, with a sum term shared across each block), 24 dedicated input pins, 10 I/O pins, 33 product terms per macrocell, asynchronous clocking per macrocell, and architectural support for D, T, JK, and SR flip-flops. The EP610 is electrically erasable, allowing in-system reprogramming via the Altera programming algorithm. The EP610PC-25 is built on a 5 V CMOS process with UV-erasable EPROM cells (the PC suffix denotes PDIP package). It supports synchronous or asynchronous register loading, programmable output enable per macrocell, and output macrocell polarity control. With 25 ns propagation delay and a 100 MHz internal pipelined data rate, it is positioned for glue-logic and interface-controller applications rather than high-density state machines. Typical applications include 5 V glue-logic replacement in microprocessor systems, address decoding for 80-series CPUs, peripheral-interface controllers (bus arbitration, interrupt controllers, custom state machines), and legacy industrial-control retrofits. The PDIP-24 footprint is socket-friendly for prototype and through-hole assembly. When designing with the EP610PC-25, allocate enough macrocell feedback for buried combinatorial logic; the AND-OR array is shared across each 16x8 block, so heavily skewed product-term distribution can limit fitting. Programming requires an Altera-compatible programmer (e.g., Altera Logic Programmer) and the MAX+PLUS II or AHDL+ toolchain. This page synthesizes distributor pricing, legacy EPLD family equivalents, and application guidance not consolidated in the original Altera datasheet.
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
The Intel / Altera EP610PC-25T is a 16-macrocell Classic EPLD (Erasable Programmable Logic Device) in the Altera Classic EP610 family, packaged in a 24-pin plastic DIP (PDIP-24) and specified for a 25 ns pin-to-pin propagation delay. It delivers 300 usable gates, 16 dedicated registers, 16 user I/Os, and pipelined data rates up to 100 MHz from a single 5 V supply, making it a compact, non-volatile logic integration point for glue-logic, bus decoding, and state-machine designs. A Classic EPLD is a one-time- or UV-programmable CMOS PLD positioned below the CPLD and FPGA tiers in the programmable-logic hierarchy. It sits architecturally between a PAL/GAL and a modern CPLD: more flexible than a fixed-AND/OR PAL, but simpler and lower-cost than a JTAG-configurable CPLD or SRAM-based FPGA. In a typical digital system the EP610 replaces multiple SSI/MSI 74LS/74HC glue-logic packages - address decoding, wait-state generation, interrupt steering - so designers reduce board area, BOM count, and assembly cost without writing HDL or purchasing a toolchain beyond a simple programmer. Key features of the EP610PC-25T include: 25 ns tPD (pin-to-pin delay, commercial speed grade), 16 macrocells each with a configurable flip-flop, product-term allocation for both combinatorial and registered logic, 5 V ±5% VCC operation, and an industry-standard JEDEC DIP-24 footprint compatible with UV-windowed EP610DC-25 ceramic parts on the same PCB. The T suffix denotes a tube-packaged shipping form, while the EP610PC-25 is shipped in tray; both share identical die and pinout. Architecturally the EP610 uses Altera's Classic macrocell with sum-of-products logic feeding a programmable output cell that can be configured as registered, combinatorial, or bi-directional I/O. The device is programmed via an industry-standard 4-pin JTAG-style interface in production programming. Its CMOS EPROM-style non-volatile configuration means no boot PROM is required, simplifying board design. Designers should be aware that the device is NOT in-system programmable and must be erased by UV light if a windowed CERDIP variant is used, or discarded if a plastic one-time-programmable (OTP) variant like the EP610PC-25T is used. Typical applications include industrial control boards, telecom line cards, legacy peripheral adapters, address decoding for microprocessors, and replacement of 74LS-series glue logic. The EP610PC-25T is also widely used for long-life-cycle embedded systems where supply continuity for over a decade is required. When designing with the EP610PC-25T, plan for a 5 V supply rail, place a 0.1 µF decoupling capacitor adjacent to each VCC pin, and budget for the OTP programming step (the device cannot be reprogrammed in-circuit). Engineers migrating from EP610PC-25 should note identical pinout, identical die, and identical speed grade. This page synthesizes distributor pricing, drop-in alternatives drawn from the Altera Classic device family, and practical design notes not found in the manufacturer datasheet alone.
EP610PC-30 - 16-Macrocell Classic EPLD, 30ns, PDIP-24 | Altera
The Altera EP610PC-30 is a 16-macrocell Classic EPLD (Erasable Programmable Logic Device) from the EP610 family, offered in a 24-pin PDIP through-hole package with a 30 ns propagation delay. It is a high-performance CMOS PLD originally designed by Altera (now Intel Programmable Solutions Group) and currently stocked and distributed by Rochester Electronics, LLC as an authorized continuing-source supplier. Classic EPLDs are a category of programmable logic devices (semiconductors) that combine AND/OR array logic with user-programmable macrocells. The Classic EPLD sits hierarchically within: programmable logic -> PLD -> EPLD -> Classic EPLD -> CMOS erasable PLD. Compared to earlier PAL/GAL devices, Classic EPLDs add output macrocells with configurable registers, feedback paths, and product-term allocation, enabling integration of multiple PAL-equivalent functions into a single chip. Key specifications of the EP610PC-30 include 300 usable gates, 16 macrocells, a 30 ns pin-to-pin propagation delay (tPD), a 33.3 MHz maximum pipeline frequency, and 5 V CMOS operation. The device supports asynchronous or synchronous clocking with dedicated input pins, provides 24 mA drive on outputs (typical), and is housed in a 24-pin 0.300-inch PDIP (Plastic Dual In-line Package) with through-hole mounting suitable for breadboarding, legacy retrofits, and industrial control equipment. The EP610PC-30 is fabricated in a 1-micron CMOS EPROM process with a quartz window option (not present on the plastic package). The architecture centers on a programmable AND array feeding an OR array into 16 output macrocells, each with a programmable register, output enable, and feedback path. Programming is performed with a standard EPROM programmer using the Altera A+PLUS or MAX+PLUS II toolchain (legacy software). The device is one-time programmable when supplied in the plastic PDIP package without a window. Typical applications include glue logic replacement for discrete 74-series TTL/CMOS gates, address decoding for 8-bit and 16-bit microprocessor systems, state-machine implementation for industrial controllers, bus-interface arbitration in legacy PC/104 and VME systems, and I/O decoding in M68000, x86, or 8051-based designs. Designers continue to use the EP610 family for long-lifecycle industrial, military, and aerospace programs where re-spinning a PCB around a modern CPLD is not feasible. When designing with this part, ensure the 30 ns tPD is compatible with the target system clock - it suits 8-25 MHz bus architectures. The device requires a single 5 V supply; a 0.1 uF decoupling capacitor placed close to VCC pin 24 is recommended. Because the EP610PC-30 is a mature product, long-lead-time planning and authorized stocking distributors should be considered for production runs. This page synthesizes Rochester Electronics distributor pricing, package-level technical data, same-family Altera EPLD drop-in alternatives, and design guidance that goes beyond what the original manufacturer datasheet alone offers.
EP610PC-30 - 16-Macrocell Classic EPLD, 30ns, PDIP-24 | Altera
The Altera EP610PC-30 is a high-performance 16-macrocell Classic EPLD (Erasable Programmable Logic Device) from the EP610 family, offering up to 100 MHz pipelined data rates in a 24-pin PDIP through-hole package. It is a CMOS, 5 V programmable logic device with 300 usable gates, 16 macrocells, and a 30 ns propagation delay (the "-30" speed grade), historically manufactured by Altera (now part of Intel) and currently sustained by Rochester Electronics as a long-term stock product. A PLD (Programmable Logic Device) is a digital integrated circuit whose internal logic structure and interconnect are user-configurable after manufacture, allowing engineers to implement custom glue logic, state machines, address decoding, and bus arbitration without committing to a custom ASIC. Within the broader taxonomy, the EP610 sits at: PLD -> EPLD (erasable, UV-window package optional) -> Classic EPLD family -> small-scale (16-macrocell) glue-logic segment. Compared to early bipolar PALs, the EP610 family added CMOS low power consumption, macrocell-based architecture (sum-of-products plus an output register), and erasable programming. Key features of the EP610PC-30 include 16 macrocells with configurable output polarity and feedback, 300 usable gates of logic capacity, pin-to-pin propagation delay of 30 ns (commercial speed grade), a maximum toggle frequency of 33.3 MHz, and an internal EPROM/EEPROM-based configuration memory (the Classic family uses UV-erasable or one-time-programmable cells). The device also exposes a dedicated JTAG/serial programming interface and supports in-system or device-programmer configuration via Altera's MAX+plus II legacy toolchain. Architecturally, the EP610 implements a programmable AND/OR array feeding 16 output macrocells, each containing a sum-of-products term generator plus a configurable D/T flip-flop. This architecture delivers deterministic, fixed-pin propagation delays (no routing-dependent timing), which simplifies timing closure in legacy 5 V designs versus early FPGAs. The classic EPLD is non-volatile - configuration is retained after power-down without external configuration memory. Typical applications include 5 V bus-interface glue logic (ISA, VME, and STD-bus address decoding), state machines for industrial control boards, peripheral chip-select generation in legacy computing platforms, parallel-port decoding, and replacement of multiple discrete 74-series TTL gates in compact through-hole designs. The PDIP-24 package is well-suited to breadboard prototyping, educational lab kits, and through-hole industrial controllers where socketed, user-replaceable logic is preferred. When designing with this part, note that the -30 speed grade trades off roughly 50 percent of toggle frequency versus the -15 grade, so verify that 33.3 MHz toggle / 30 ns pin-to-pin delay is sufficient for the target clock domain. For modern 3.3 V or lower-voltage systems, a level translator or a current-generation MAX II / MAX V CPLD is recommended. This page synthesizes distributor pricing, same-family and cross-family drop-in alternatives, and practical design notes not found in the original 1990s Altera datasheet, helping engineers source this legacy part reliably.
EP610PC-35 - 16-Macrocell Classic EPLD, 35ns tPD | Rochester
The Rochester Electronics EP610PC-35 is a legacy-sustained 16-macrocell Classic EPLD (Erasable Programmable Logic Device) housed in a 24-pin PDIP through-hole package. It offers 300 usable gates, a 37ns pin-to-pin propagation delay (tPD) under the -35 speed grade, and pipelined data rates of up to 100 MHz on internal registered paths. The device is built on a 5V CMOS UV-erasable process and belongs to the original Altera Classic EPLD family that has been second-sourced by Rochester Electronics to support long-life-cycle and legacy systems. A Classic EPLD is a programmable logic device from the first generation of CMOS PLDs, combining macrocell-based logic, deterministic timing, and non-volatile (UV-erasable) configuration. EP610-class parts sit in the broader taxonomy of programmable logic devices (PLDs), which include simple PAL/GAL devices at the low end, CPLDs in the middle, and FPGAs at the high end. EP610PC-35 belongs to the low-density CPLD/EPLD tier, suitable for glue logic, address decoding, bus arbitration, and state-machine replacement in industrial, military, and avionics systems designed in the late 1980s and 1990s. Key features include 16 macrocells, 300 gates of usable logic, 35ns worst-case tPD, 100 MHz internal fCNT, 5V ±5% supply operation, and JEDEC-standard 24-pin PDIP packaging. The device supports synchronous and asynchronous clocking, programmable I/O architecture with output enable, and a 100% factory-tested AC performance specification. The -35 speed grade positions this part at the slower end of the EP610 family; faster -25 and -20 grades exist for timing-critical paths. Technically, the EP610 family uses a Classic macrocell architecture with sum-of-products logic feeding a programmable output register. The 24-pin PDIP footprint is a JEDEC-standard 0.600" wide plastic DIP with through-hole leads, making the EP610PC-35 suitable for socketed designs, hand-prototyping breadboards, and legacy board repair. Parts are tested and re-qualified by Rochester Electronics against the original Altera specifications to provide form-fit-function continuity. Typical applications include legacy industrial control replacement, address decoding for 8/16-bit microprocessor buses, state-machine implementation for instrumentation, and pin-compatible second-source for end-of-life designs. The UV-erasable window variant (EP610DC) and one-time-programmable plastic versions share the same logic and timing. When designing with this part, note that it is not pin-compatible with modern low-voltage CPLDs (3.3V or 1.8V). Use it only where 5V I/O, original Altera EP610 footprints, or long-term military/industrial sustainment programs require it. Modern low-cost alternatives from Lattice (GAL/iCE40) require PCB rework. This page synthesizes distributor pricing, Rochester sustainment lead times, and practical cross-references not found in the original Altera datasheet, with drop-in alternatives sourced from verified EP610-family listings.
EP610PC25 - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Altera
The Altera EP610PC25 is a 16-macrocell Classic-series Erasable Programmable Logic Device (EPLD) in a 24-pin plastic DIP (PDIP-24) package, with a propagation delay of 25 ns and pipelined data rates up to 100 MHz. Fabricated in 5 V CMOS, this OTP-EPLD delivers 300 usable gates of low-density glue logic in a through-hole form factor still favored for legacy industrial, instrumentation, and educational designs. The Classic EPLD architecture combines AND/OR logic with per-macrocell flip-flops, making it functionally similar to a small array of PAL-type devices integrated into a single package. An EPLD (Erasable Programmable Logic Device) is a one-time- or UV-programmable non-volatile logic device that preceded modern CPLDs and FPGAs. EPLDs sit in the PLD hierarchy above simple PAL/GAL devices but below today's high-density FPGAs - useful as glue logic, address decoding, state machines, and bus interface controllers. Within the broader taxonomy, EPLDs fall under programmable logic devices (PLDs) -> CPLDs -> programmable semiconductors, and they share architecture with later MAX-series CPLDs while retaining the Classic-series' distinctive 24-pin PDIP footprint. Key features of the EP610PC25 include 16 macrocells (each with a programmable flip-flop), 24 dedicated input pins, 16 output pins, and pin-compatible JEDEC-standard programming via standard device programmers. The 25 ns tPD allows clocked logic up to ~40 MHz (synchronous), while pipelined internal paths support up to 100 MHz. Power consumption is approximately 200 mA ICC at 5 V, and the device operates over the commercial 0C to +70C range. The PDIP-24 through-hole package allows easy socket-mounting and rework, valuable in lab and production-line environments. Architecturally, the EP610PC uses a sum-of-products AND-OR logic array feeding 16 macrocells, each with a configurable D/T/JK flip-flop and output enable. Inputs feed through a global interconnect to the AND array, and outputs drive bidirectional I/O pins. Programming is performed via a standard JEDEC fuse map on a device programmer using Altera's classic flow. The Classic EPLD family was a precursor to the MAX 7000/5000-series CPLDs that subsequently dominated low-density programmable logic. Typical applications include address decoding for 8-bit and 16-bit microprocessors, glue logic for peripheral interfacing, state machines in industrial controllers, bus arbitration logic in VME/ISA-style backplanes, and replacement of multiple discrete 74LS/74HC TTL gates in legacy systems. The DIP-24 footprint makes it popular in educational lab kits and in long-life-cycle equipment where surface-mount migration is undesirable. When designing with this device, note that it requires a 5 V supply and a programming voltage of 12 V on the VPP pin. A proper decoupling scheme (100 nF + 10 uF bulk) near the supply pins is mandatory, and unused inputs should be tied to ground through a resistor or to VCC to prevent floating inputs. Designers transitioning from the EP610PC to newer logic should consider the pin-compatible LC/LI/DC speed grades or migrating to a modern MAX II CPLD in a JTAG-programmable package.
EP610PI-25 - 16-Macrocell Classic EPLD, 25ns DIP-24 | Rochester
The Rochester Electronics EP610PI-25 is a member of the Altera Classic EP610 family of Erasable Programmable Logic Devices (EPLDs), supplied in a 24-pin ceramic DIP (PI) through-hole package with a 25 ns pin-to-pin propagation delay. It integrates 16 macrocells and approximately 300 usable gates of combinational and sequential logic on a single CMOS die, making it a compact glue-logic replacement for multiple 74LS/74HC discrete devices in legacy industrial, telecom, and instrumentation designs. A Programmable Logic Device (PLD) is a general-purpose digital IC whose logic function is defined after manufacture by the user, sitting in the broader hierarchy of programmable logic between simple PAL/GAL arrays and modern CPLD/FPGA fabrics. The Classic EP610 family represents an early generation of CMOS UV-erasable EPLDs that consolidated several PAL-equivalent macrocells into a single AND/OR array with per-macrocell flip-flop and output enable control. The 'P' suffix designates the plastic/ceramic DIP package, the 'I' indicates the industrial operating temperature range, and the '-25' suffix specifies the 25 ns tPD speed grade, which is the slowest of the family and well suited to bus-interface and control-logic applications running below ~40 MHz. Key features of the EP610PI-25 include 16 macrocells, four dedicated inputs, 16 bidirectional I/O pins in the 24-pin DIP, output macrocell flip-flops with configurable D/T/JK/SR modes, programmable output enable per macrocell, and a single global clock. Architecture is based on a sum-of-products (AND-OR) PLA with each macrocell feeding one bidirectional I/O pin. The device is non-volatile (UV-erasable) and offers deterministic 25 ns propagation delay that does not depend on routing density, an advantage over later channel-routed CPLDs. Power consumption is typically under 200 mW at 5 V, and the part is 100% pin-compatible with the EP610PI-20 and EP610PI-15 faster speed grades, allowing direct in-circuit speed upgrade. Typical applications include legacy bus-interface decoding (8086, 68000, Z80 address decode and glue logic), industrial control state machines, telecommunications channel-bank control, instrumentation address decoding, and as a pin-compatible replacement for multiple PAL/GAL devices in legacy aerospace and military systems. The DIP-24 through-hole footprint also supports easy breadboarding and socketed replacement in maintenance scenarios. When designing with the EP610PI-25, use the Altera MAX+PLUS II (legacy) or A+PLUS development environment for schematic/VHDL/Verilog entry, and ensure the JTAG/programming socket allows UV erasure (windowed packages). Provide a clean 5 V ±5% supply and decouple VCC with a 0.1 µF ceramic capacitor adjacent to the IC. Note that modern 5 V-tolerant CPLDs such as the MAX II family offer much higher density but at a different pinout; the EP610PI-25 is a true drop-in for legacy EP610 designs only. This page synthesizes legacy Rochester Electronics distributor pricing, drop-in EP610 family alternatives that share the DIP-24 footprint, and practical design notes for maintaining legacy EPLD designs not found in the original Altera datasheet.
EP610PI-30 - 16-Macrocell Classic EPLD, 30ns, PDIP-24
The Intel (originally Altera) EP610PI-30 is a high-performance Classic EPLD (Erasable Programmable Logic Device) in the EP610 family, packaged in a 24-pin PDIP with 16 macrocells, 300 usable gates, and a 30 ns pin-to-pin propagation delay. It is built on CMOS EEPROM technology, is one-time-user-programmable (UV-erasable windowless package), and supports pipelined data rates up to 100 MHz while consuming only CMOS-level standby current. A Classic EPLD is an early-generation programmable logic device that sits between discrete 74-series glue logic and modern CPLDs/FPGAs in the programmable logic hierarchy: discrete logic -> PAL/GAL -> EPLD -> CPLD -> FPGA -> SoC FPGA. The EP610 family replaced fuse-link bipolar PALs with CMOS EEPROM cells, providing reprogrammability, lower power, and predictable timing - the macrocell architecture gives every output a fixed, deterministic propagation delay independent of logic complexity, which is the key advantage over early FPGAs. Key features of the EP610PI-30 include 16 macrocells, 4 dedicated inputs, 10 I/O pins, 2 global clock inputs, in-system programmable EEPROM configuration memory, and a 5 V single supply with CMOS/TTL-compatible I/O. The PI-30 speed grade corresponds to a 30 ns tPD (worst-case commercial), making the part suitable for asynchronous glue-logic replacement, address decoding, state-machine control, and bus-interface adaptation up to roughly 33 MHz non-pipelined / 100 MHz pipelined operation. Architecturally the EP610 uses sum-of-products logic feeding output macrocells with programmable register/bypass modes, plus a global interconnect. Because every macrocell has a fixed, deterministic delay, the device eliminates the place-and-route timing closure step that complicates FPGA design - the user simply writes Boolean equations and the timing is known by inspection. The EEPROM process retains the bitstream for 20+ years and supports 100+ reprogram cycles. Typical applications include asynchronous state-machine controllers in industrial PLCs, address-decoding and chip-select logic in 5 V microcomputer systems, bus arbitration and glue logic between 8/16-bit microprocessors and peripherals, and replacement of legacy 74LS/74F series TTL gate arrays. Designers often select the EP610 family to consolidate dozens of SSI/MSI packages onto a single, factory-programmed part. When designing with the EP610PI-30, ensure that all inputs respect the 5 V CMOS/TTL logic thresholds (VIL <= 0.8 V, VIH >= 2.0 V) and that outputs are not loaded beyond the 24 mA sink/source rating per pin. A 0.1 uF decoupling capacitor should be placed within 5 mm of the VCC pin. Programming requires an Altera/Intel-compatible device programmer such as the Altera MAX+PLUS II flow; this device is no longer recommended for new designs but remains supported by Rochester Electronics as a long-life buy. This page synthesizes distributor stock, parametric cross-references, and practical design notes beyond the original manufacturer datasheet to help engineers evaluate, source, and apply the EP610PI-30 in legacy 5 V systems.
EP610SC-15 - 16-Macrocell Classic EPLD, 15ns tPD | Altera (Intel)
The Altera (now Intel) EP610SC-15 is a member of the Altera Classic EPLD family, integrating 300 usable gates and 16 macrocells into a 24-pin small-outline (SOP/SOIC-24) package with a 15 ns pin-to-pin propagation delay. Operating from a single 5 V supply (4.75 V to 5.25 V), the part provides a CMOS-compatible, UV-erasable EPLD architecture intended for high-speed, low-power logic integration that replaces multiple TTL/CMOS SSI/MSI gates. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device sitting between simple PAL/GAL architectures and modern FPGAs/CPLDs in the programmable logic hierarchy. The Classic family uses a sum-of-products AND/OR structure with a programmable macrocell, allowing designers to implement glue logic, state machines, address decoding, and bus interfacing in a single chip that retains its configuration when power is removed. This product category sits between discrete 74-series logic gates and modern complex programmable logic devices (CPLDs), offering deterministic 15 ns timing without the need for JTAG or in-system programming. Key features include a maximum operating frequency in the tens of MHz range (fMAX around 83 MHz typical for the -15 speed grade), 24 input/output pins, 16 macrocells, low CMOS standby current, and a JEDEC-standard 24-pin 300-mil SOIC package. The part supports both combinatorial and registered logic modes through its macrocell flip-flop, with independent feedback paths into the AND array. Programming is performed via a standard EPROM-style algorithm and the configuration is erased with a UV window (the ceramic-windowed variants such as the EP610LC series), while the 'SC' commercial plastic package is one-time-programmable for production volumes. Typical applications include TTL/CMOS logic replacement, bus address decoding and chip-select generation, state machines for peripheral controllers, encoder/decoder logic, and interface glue between microprocessors and peripherals. Its deterministic 15 ns timing and 5 V interface make it especially suitable for legacy industrial control boards, telecommunications backplane cards, and instrumentation front-ends that require bus-interface logic without software-driven PLD configuration. When designing with the EP610SC-15, ensure that the 24-pin SOP land pattern matches the JEDEC SO-24 300-mil footprint. Decoupling should include a 0.1 µF ceramic capacitor as close as possible to the VCC and GND pins. Designers migrating to lower-density CPLDs from Lattice or Xilinx should verify pinout compatibility because the EP610's pin ordering is specific to the Classic family. This page consolidates distributor pricing, drop-in speed-grade alternatives within the EP610 family, and practical design notes beyond the manufacturer datasheet.