EP610LI-20 - Classic 16-Macrocell EPLD, 20ns | Rochester/Altera
부품 번호: EP610LI-20 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $28.4123 | $28.41 |
| 10 | $25.57 | $255.70 |
| 100 | $22.73 | $2,273.00 |
| 500 | $20.5 | $10,250.00 |
| 1,000 | $18.2 | $18,200.00 |
EP610LI-20 개요
What is a Classic EPLD? An Erasable Programmable Logic Device is a UV-erasable, electrically programmable logic IC that preceded modern CPLDs and FPGAs. Conceptually, an EPLD sits in the programmable logic hierarchy as follows: programmable logic device (PLD) -> EPLD (UV-erasable) -> CPLD (modern non-volatile equivalent) -> FPGA (largest, SRAM-based). Each Classic EPLD macrocell combines a programmable AND-OR array with a flip-flop, allowing replacement of multiple SSI/MSI glue-logic packages with a single reprogrammable device.
Key features of the EP610LI-20 include 16 macrocells, 24 dedicated input pins, 20 I/O pins, a maximum toggle frequency of 100 MHz, 20 ns tPD (pin-to-pin) at worst-case commercial conditions, and CMOS technology with low standby current. The 'LI' suffix denotes the industrial temperature range (-40C to +85C) and 20 ns speed grade, while the 'L' package suffix indicates a PLCC (Plastic Leaded Chip Carrier) JEDEC outline.
The EP610LI-20 implements a sum-of-products AND-OR array per macrocell with an output flip-flop and a programmable output enable. Architecturally, it offers predictable, deterministic timing suitable for replacing PAL/GAL devices with higher macrocell density. The device is programmed using a standard Altera programming algorithm via dedicated programming hardware.
Typical applications include industrial control glue logic, address decoding for legacy microprocessor boards (Intel 8086/8088, Motorola 68k), bus-interface adaptation, state-machine replacement, and prototyping of discrete SSI/MSI logic functions. The PLCC-28 socket-compatible footprint also enables direct substitution onto existing Altera EP610, EP610I, and EP910 boards when pin-compatible speed grades are required.
When designing with the EP610LI-20, ensure the supply rail is decoupled with 0.1 uF ceramic capacitors close to each VCC pin and that unused inputs are tied to VCC or GND to avoid oscillation. Because the part is UV-erasable, designs requiring field re-programmability must include a windowed (ceramic) package variant or migrate to a modern MAX-series CPLD for in-system programmability.
This page synthesizes distributor pricing, same-brand Altera/Rochester EP610 family drop-in alternatives, and practical design notes not collated in the original datasheet, helping engineers sourcing legacy EPLDs extend the lifecycle of installed equipment without PCB rework.
드롭인 대체품: EP610LI-20 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP610LI-20 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Family, Operating Temperature, Programming Method, Mounting Type.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP610LI-15
✅ 드롭인✓ 재고 있음
$48.5 / 개
데이터시트 보기 →EP610LC-25
✅ 드롭인✓ 재고 있음
$6.2 / 개
데이터시트 보기 →EP610LC-15
✅ 드롭인✓ 재고 있음
$4.65 / 개
데이터시트 보기 →EP610ILC-10
✅ 드롭인✓ 재고 있음
$7.2 / 개
데이터시트 보기 →EP610ILC-25
✅ 드롭인✓ 재고 있음
$9.85 / 개
데이터시트 보기 →EP610DM/883B
✅ 드롭인✓ 재고 있음
$87.2 / 개
데이터시트 보기 →EP610LI-20 최대 정격 & 전기적 특성
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EP610 |
| Macrocells | 16 |
| Propagation Delay (tPD) | 20 ns |
| Maximum Toggle Frequency | 100 MHz |
| Supply Voltage (VCC) | 4.5 V to 5.5 V |
| Technology | CMOS, UV-erasable |
| 패키지 | 28-pin PLCC (PQCC28 / JEDEC MO-047) |
| 동작 온도 | -40 C to +85 C (industrial, 'I' suffix) |
| Speed Grade Suffix | -20 = 20 ns tPD |
| Temperature Grade Suffix | L = Low-power/industrial |
| 실장 유형 | Surface Mount (PLCC socket compatible) |
| Programming Method | Altera EP610 programmer (legacy) |
| Distributor Stock Indicator | Available via Rochester Electronics authorized channel |
EP610LI-20 핀 구성
| 핀 1 | I/O — Input/Output macrocell 1 |
| 핀 2 | I/O — Input/Output macrocell 2 |
| 핀 3 | I/O — Input/Output macrocell 3 |
| 핀 4 | I/O — Input/Output macrocell 4 |
| 핀 5 | I/O — Input/Output macrocell 5 |
| 핀 6 | I/O — Input/Output macrocell 6 |
| 핀 7 | I/O — Input/Output macrocell 7 |
| 핀 8 | I/O — Input/Output macrocell 8 |
| 핀 9 | I/O — Input/Output macrocell 9 |
| 핀 10 | I/O — Input/Output macrocell 10 |
| 핀 11 | I/O — Input/Output macrocell 11 |
| 핀 12 | I/O — Input/Output macrocell 12 |
| 핀 13 | I/O — Input/Output macrocell 13 |
| 핀 14 | GND — Ground |
| 핀 15 | I/O — Input/Output macrocell 14 |
| 핀 16 | I/O — Input/Output macrocell 15 |
| 핀 17 | I/O — Input/Output macrocell 16 |
| 핀 18 | INPUT — Dedicated input pin |
| 핀 19 | INPUT — Dedicated input pin |
| 핀 20 | INPUT — Dedicated input pin |
| 핀 21 | INPUT — Dedicated input pin |
| 핀 22 | INPUT — Dedicated input pin |
| 핀 23 | INPUT — Dedicated input pin |
| 핀 24 | INPUT — Dedicated input pin |
| 핀 25 | INPUT — Dedicated input pin |
| 핀 26 | INPUT — Dedicated input pin |
| 핀 27 | INPUT — Dedicated input pin |
| 핀 28 | VCC — +5 V supply voltage |
일반적인 애플리케이션
EP610LI-20 적합 용도: 6 애플리케이션s: Legacy Industrial Control Glue Logic, Microprocessor Address Decoding, Bus Interface Adaptation (ISA/VME), State Machine Replacement, SSI/MSI Logic Consolidation, Legacy Equipment Sustaining Maintenance.
Legacy Industrial Control Glue Logic
The EP610LI-20 fits industrial control glue-logic applications that require deterministic, predictable timing for replacing discrete 74LS/74HC SSI/MSI packages. With 16 macrocells and 20 ns tPD, it replaces multiple 22V10-class PAL/GAL devices, reducing PCB area and BOM count in legacy PLC and process-control designs. The industrial temperature range (-40 C to +85 C) ensures reliable operation in factory-floor environments, while the PLCC-28 socket allows field replacement without desoldering. Companion logic: 74LS245 bus transceivers and 74LS374 octal latches for buffered I/O.
추천
Microprocessor Address Decoding
The EP610LI-20 fits 8086/8088/68k microprocessor address-decoding applications where 16 macrocells provide sufficient product-term density to decode full 16- or 20-bit address buses into chip-select outputs. With 20 ns tPD it satisfies address-to-CS timing requirements for 8 MHz and most 12 MHz processor designs. The 28-pin PLCC footprint sits alongside the CPU and memory devices, replacing 2-4 discrete decoder PALs. Companion parts: 8086 CPU, 62256 SRAM, EPROM for address space expansion.
추천
Bus Interface Adaptation (ISA/VME)
The EP610LI-20 fits legacy ISA and VME bus-interface adaptation applications where its 20 ns tPD satisfies bus arbitration and chip-select timing without introducing wait states. The 16 macrocells accommodate signal-level translation, control-signal generation, and interrupt-priority encoding between peripheral ICs and the host bus. Industrial temperature rating suits factory-automation backplanes. Companion chips: 74LS245 transceivers, 74LS138 decoders, and bus-termination networks for robust signaling.
추천
State Machine Replacement
The EP610LI-20 fits state-machine replacement applications in legacy instrumentation, motor-control, and protocol-converter designs where its 16 macrocells implement 16-state Mealy or Moore machines with deterministic 20 ns transition delays. Each macrocell's flip-flop stores one state bit, while the AND-OR array encodes transition logic. The PLCC-28 socketed footprint supports field firmware updates via UV-erase window (ceramic-package variant). Companion: HCMOS crystal oscillator and reset supervisor.
추천
SSI/MSI Logic Consolidation
The EP610LI-20 fits SSI/MSI logic consolidation applications where designers replace 4-8 standard 74LS/74HC packages (gates, multiplexers, latches, decoders) with a single EPLD to reduce PCB area, power consumption, and assembly cost. With 16 macrocells the EP610LI-20 typically replaces 30-50 equivalent gates while maintaining 20 ns propagation delay for moderate-speed logic paths. The PLCC-28 package fits standard IC sockets, simplifying drop-in consolidation on legacy boards.
추천
Legacy Equipment Sustaining Maintenance
The EP610LI-20 fits legacy equipment sustaining-maintenance applications in industrial automation, military systems, and avionics where original Altera EP610 EPLDs have reached end-of-life but the host equipment must remain operational for decades. Rochester Electronics' authorized sustaining-distribution model guarantees long-term EP610 family availability with original Altera datasheet compliance. The PLCC-28 socketed footprint enables direct board swap without PCB modification, preserving Form-Fit-Function of the host system.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP610LI-20 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP610LI-15 | EP610LC-25 | EP610LC-15 | EP610ILC-10 | EP610ILC-25 | EP610DM/883B |
|---|---|---|---|---|---|---|---|
| Package | 28-pin PLCC (PQCC28) | 28-pin PLCC (PQCC28) - same | 28-pin PLCC (PQCC28) - same | 28-pin PLCC (PQCC28) - same | 28-pin PLCC (PQCC28) - same | 28-pin PLCC (PQCC28) - same | 28-pin PLCC (PQCC28) - same |
| Brand | Rochester Electronics | Rochester Electronics | Rochester Electronics | Rochester Electronics | Rochester Electronics | Rochester Electronics | Rochester Electronics |
| Propagation Delay (tPD) | 20 ns | 15 ns | 25 ns | 15 ns | 10 ns | 25 ns | 20 ns |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
| Temperature Grade | Industrial (-40 C to +85 C) | Industrial (-40 C to +85 C) | Commercial (0 C to +70 C) | Commercial (0 C to +70 C) | Industrial (-40 C to +85 C) | Industrial (-40 C to +85 C) | Military (-55 C to +125 C) |
| Supply Voltage | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| Maximum Toggle Frequency | 100 MHz | 100 MHz | 83.3 MHz | 100 MHz | 125 MHz | 83.3 MHz | 100 MHz |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable | CMOS, UV-erasable | CMOS, UV-erasable | CMOS, UV-erasable | CMOS, UV-erasable | CMOS, UV-erasable |
주요 차별점
- Rochester Electronics authorized sustaining-distribution channel (vs EP610LI-15)
- Industrial temperature grade at standard speed (vs EP610LC-25)
- Military screening option available in same package (vs EP610DM/883B)
설계 노트
Decouple the EP610LI-20 with a 0.1 uF ceramic capacitor placed within 5 mm of each VCC pin (pin 28), and add a bulk 10 uF tantalum or aluminum electrolytic capacitor on the 5 V supply rail. The EP610 family draws CMOS-class supply current (typically tens of mA active, low-uA standby), so a clean 5 V rail is critical. Avoid sharing the EPLD's VCC with high-current switching loads without local LC filtering.
Tie all unused dedicated input pins (pins 18-27 in the PLCC-28 package) directly to VCC or GND - never leave them floating - because floating CMOS inputs can oscillate and cause excessive supply current. Similarly configure unused I/O pins via the EP610 programmer as outputs driving a defined logic level. This prevents spurious switching noise that can corrupt adjacent macrocell behavior.
Route EP610LI-20 outputs through series damping resistors (22-33 ohm) when driving long PCB traces or capacitive loads above 50 pF to limit ground-bounce and edge-rate-induced ringing. The 20 ns tPD produces fast CMOS edges that couple readily into adjacent signal traces. Maintain a ground plane under the EPLD footprint and keep clock inputs short and guarded to preserve deterministic macrocell timing.
규정 준수 정보
RoHS/REACH/lead-free status not confirmed in the verified web data; legacy Altera Classic EPLDs from the 1980s-1990s predate RoHS directives. Marked [DATA_NEEDED] in specs. Military-grade EP610DM/883B variant available for MIL-STD-883 applications.
