FPGA & CPLD
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EPM7160ELC84-20 - MAX 7000 CPLD, 160 Macrocells, 20ns | Intel
The Intel EPM7160ELC84-20 is a high-density, high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000 family, featuring 160 macrocells, 4 Logic Array Blocks, and 64 user I/O pins housed in an 84-pin PLCC (Plastic Leaded Chip Carrier) package. The device is built on Altera's second-generation MAX architecture and supports 5.0-V in-system programmability (ISP) via the built-in IEEE Std. 1149.1 JTAG interface, enabling rapid prototyping and field upgrades without removing the part from the board. The "20" suffix indicates a 20 ns pin-to-pin logic delay, making it well suited to glue-logic, bus interfacing, and state-machine applications running at moderate clock rates. A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on programmable logic device that combines the architecture of multiple PAL/GAL-like PLDs on a single chip with a programmable interconnect matrix. CPLDs occupy the middle ground between small discrete logic ICs (gates, muxes, flip-flops) and larger FPGAs: they offer deterministic timing, sub-100 ns propagation delays, and zero configuration time at power-up. In the broader system hierarchy, the MAX 7000 CPLD sits between 74-series discrete logic and SRAM-based FPGAs, serving as the ideal integration point for board-level glue logic, address decoding, interrupt steering, and I/O expansion. The MAX 7000 series is a foundational product line that helped popularize ISP and JTAG-based programming in mainstream digital design. Key features include 3,200 usable gates, 64 I/O pins with 5-V tolerant I/O on most variants, four global clock inputs, and a JTAG-compliant boundary-scan test interface. The device operates from a single 5.0 V supply (VCCINT and VCCIO combined) with low standby current, and supports commercial (0C to +70C) operating temperature ranges. Programming is performed via the JTAG port using the ByteBlaster or BitBlaster download cable, or in-system from a microcontroller-driven JTAG master, eliminating the need for a dedicated programmer. Typical applications include peripheral glue logic in microprocessor and DSP systems, address decoding and chip-select generation, bus arbitration and interrupt prioritization, register-based I/O expansion, and JTAG-driven board-level test infrastructure. The 84-pin PLCC package is socket-friendly, supporting both production assembly and easy breadboard prototyping for engineering development. When designing with this device, designers should provide adequate decoupling (typically 0.1 uF per VCC pin plus a 10 uF bulk capacitor) and follow Altera's JTAG chain recommendations when multiple devices share the same programming port. The PLCC-84 footprint is a JEDEC-standard land pattern, but designers migrating to lead-free assemblies should verify the soldering profile against the JEDEC J-STD-020 moisture sensitivity level (MSL) rating. This page synthesizes distributor pricing, drop-in alternatives within the same PLCC-84 footprint, and practical design notes not found on a single manufacturer page.
EPM7160ELI84-20 - MAX 7000 CPLD, 160 Macrocells, 5V, 84-PLCC | Intel
The Intel EPM7160ELI84-20 is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000 family, featuring 160 macrocells, 3.2K usable gates, and a 62.5 MHz maximum operating frequency, housed in an 84-pin Plastic Leaded Chip Carrier (PLCC) package. It is built on Altera's second-generation MAX architecture with EEPROM-based non-volatile configuration cells that retain logic when power is removed, and supports 5.0-V in-system programmability (ISP) via the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that sits between simple PAL/GAL devices and high-density FPGAs in the programmable logic hierarchy. CPLDs are typically used for glue logic, bus interfacing, state-machine control, and power-up sequencing in digital systems where deterministic timing, fast input-to-output propagation, and instant-on behavior are required. The MAX 7000 family is one of the longest-lived CPLD families in the industry, having shipped continuously since the 1990s in industrial, telecommunications, and embedded designs. Key features of the EPM7160ELI84-20 include 64 user I/O pins organized into four Logic Array Blocks (LABs), a pin-to-pin propagation delay of 20 ns (the '-20' speed grade), 5.0V core VCC operation, and programmable power-saving mode on a per-macrocell basis. The device also offers open-drain output options, programmable security bits for design protection, and JTAG boundary-scan test support per IEEE 1149.1. Architecturally, the EPM7160ELI84-20 uses a classic MAX-style AND-OR plane with a programmable interconnect array (PIA) that provides deterministic, consistent routing delays across all logic paths, simplifying static timing closure compared to FPGAs. Each macrocell contains a programmable flip-flop, product-term selection logic, and a configurable I/O register, enabling efficient implementation of wide combinatorial and registered logic. Typical applications include industrial control and factory-automation boards, telecommunications line cards and legacy backplane glue logic, PCI bus interface bridges, address decoding and interrupt controllers in embedded CPU designs, and replacement of multiple discrete 74LS/74HC logic devices on legacy PCBs. The instant-on, non-volatile nature of the MAX 7000 family makes it especially attractive for safety-critical boot logic and deterministic control. When designing with this device, plan I/O assignments early - the 84-pin PLCC exposes 64 usable I/Os and four dedicated JTAG/programming pins, so not all 84 pins are user I/O. Use the Altera/Intel Quartus (or legacy MAX+PLUS II) toolchain for synthesis, fitting, and programming, and respect the 5.0V VCC requirement when mixing with 3.3V logic (the I/Os are 5V-tolerant inputs but cannot drive 3.3V outputs above their VCCIO). This page synthesizes distributor stock status, the same-brand MAX 7000 family drop-in variants, and practical design considerations not found in the manufacturer datasheet, helping engineers make informed decisions about lifecycle status and replacement strategy for this mature, long-running CPLD.
EPM7160EQC100-20 - MAX 7000 CPLD, 160 Macrocells, 100-Pin PQFP
The Altera (now Intel) EPM7160EQC100-20 is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000 family, housed in a 100-pin Plastic Quad Flat Pack (PQFP) package. The device integrates 3,200 usable gates, 160 macrocells, and 84 user I/O pins with a 20 ns pin-to-pin propagation delay (corresponding to a 62.5 MHz internal frequency). It is built on Altera's second-generation MAX architecture, which combines the density and register-rich structure of high-density PLDs with the in-system programmability and familiar MAX development flow. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits in the broader hierarchy of programmable logic: it is a sibling of the simpler SPLD and an ancestor of the modern FPGA and CPLD sub-classes. The MAX 7000 family targets glue-logic, bus-interface, control-plane, and high-drive applications where deterministic timing and instant-on non-volatile configuration are required. Designers use MAX 7000 parts for decoding, address mapping, state-machine implementation, and bus arbitration in systems where an FPGA would be overkill or where fast, predictable propagation delay is essential. Key features of the EPM7160EQC100-20 include configurable 3.3 V or 5 V I/O operation (5 V nominal core supply), an Enhanced Quad Flat Pack (EQFP) form factor, and commercial temperature-grade operation. The 'E' suffix indicates an enhanced configuration mode for fast in-system programming, while 'QC100' denotes the 100-pin PQFP package, and '-20' specifies the 20 ns speed grade. The CPLD supports the IEEE 1149.1 boundary-scan (JTAG) interface and uses 4-pin JTAG ISP for in-system programming. According to the Altera MAX 7000 datasheet, the device can be erased and reprogrammed in-system up to 100 times, and configuration is non-volatile via on-chip EEPROM. The MAX architecture uses a classic Logic Array Block (LAB) / Programmable Interconnect Array (PIA) topology, where each macrocell is fed by a 36-input AND-style product term array and registered feedback. The macrocell contains a programmable flip-flop with selectable clear, preset, clock, and clock-enable signals, supporting D, T, JK, and SR flip-flop operation. The macrocell can also be configured for combinational logic when registers are not required, allowing the designer to allocate logic and register resources where they are needed most. Typical applications include peripheral interface bridging (e.g., connecting a microcontroller to legacy parallel ports), bus decode and chip-select generation for microprocessors, asynchronous state-machine controllers, and high-drive bus-buffer or level-translation between 3.3 V and 5 V domains. Designers also deploy the EPM7160EQC100-20 in industrial control systems, telecom glue logic, and retrofit boards that must match a legacy 100-pin PQFP footprint. The 84 available I/Os are sufficient for medium-complexity glue-logic, and the 5 V-tolerant I/Os ease mixed-voltage interfacing. When designing with this device, allow at least 1 ms after power-up before JTAG programming and provide a clean 5 V supply with 100 nF + 10 uF decoupling close to the VCC pins. The PQFP-100 footprint requires careful soldering or socket use; engineers evaluating modern replacements should consider MAX II or MAX V devices in smaller QFP or BGA packages for new designs. This page synthesizes distributor pricing, drop-in alternatives drawn from the same Altera MAX 7000 family, and practical design notes that go beyond the manufacturer datasheet alone.
EPM7160EQC160-12 - 160-Macrocell MAX 7000 CPLD | Intel | 5V ISP
The Intel (formerly Altera) EPM7160EQC160-12 is a high-density, EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000E family, providing 160 macrocells across 4 Logic Array Blocks with 104 user I/O pins in a 160-pin PQFP (EQC) package. It features 12 ns pin-to-pin logic delay and a 5.0-V in-system programmability (ISP) interface via the built-in IEEE Std. 1149.1 JTAG boundary-scan port. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell arrays on a single chip with a global interconnect matrix. CPLDs sit in the programmable logic hierarchy between small SPLDs (typically a few macrocells) and large FPGAs, offering deterministic timing, instant-on operation from on-chip EEPROM, and high fan-in / fan-out capability. They are widely used as glue logic, bus interface bridges, and state-machine controllers in industrial, telecom, and automotive systems. The EPM7160EQC160-12 delivers 3,200 usable gates, four global clock signals with additional output enable controls, fast input registers, and an enhanced interconnect fabric that improves routability versus the original MAX 7000S family. Its 5 V tolerant I/O and commercial 0 °C to +70 °C operating range make it well suited to legacy 5 V system designs. The device is non-volatile - configuration is retained without external memory and is reprogrammable in-circuit through JTAG. The MAX 7000E architecture pairs each macrocell with a product-term array that feeds into a programmable register, with each LAB (Logic Array Block) sharing 36 macrocells and an I/O block of 36 signals. This balanced architecture yields predictable, fixed propagation delays that are critical for address decoding, interrupt steering, and synchronous state machines where FPGAs would be over-specified. Typical applications include 5 V bus interfacing (ISA, VME, parallel port), industrial control glue logic, peripheral controllers, and drop-in upgrades for older discrete TTL/CMOS logic. Designers favor the EPM7160EQC160-12 when they need a non-volatile, JTAG-reprogrammable logic block with deterministic timing and a PQFP-160 footprint compatible with long-lived industrial designs. A key design tip: the PQFP-160 package has relatively high thermal resistance - keep switching frequencies moderate and observe the 5 V VCCIO decoupling guidelines (0.1 µF + 10 µF bulk per VCC pin pair). The JTAG TCK maximum frequency of 10 MHz governs ISP programming time; budget approximately 2-5 seconds for full device erase-and-program. This page synthesizes distributor stock data, drop-in alternatives from the same MAX 7000E family, and design notes not found in the original Altera datasheet to help engineers select, source, and integrate the EPM7160EQC160-12 quickly.
EPM7160SLC84-10 - 160-Macrocell MAX 7000S CPLD | Altera
The Altera EPM7160SLC84-10 is a high-density, 5.0-V in-system programmable Complex Programmable Logic Device (CPLD) from the second-generation MAX 7000S family, delivering 160 macrocells, 4 Logic Array Blocks (LABs), and 64 user I/O pins in an 84-pin PLCC (J-Lead) package with a 10 ns pin-to-pin propagation delay. Built on EEPROM-based MAX architecture, the device offers 3,200 usable gates and a maximum operating frequency of 100 MHz, making it suitable for high-speed glue-logic, bus interfacing, and state-machine implementation. Programmable through the built-in IEEE Std. 1149.1 JTAG interface, the EPM7160SLC84-10 supports 5.0-V in-system programmability (ISP) that allows on-board configuration without removing the part, enabling field upgrades and rapid prototyping. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic device that combines multiple PAL-like macrocells with a central interconnect matrix. CPLDs sit between simple SPLDs/GALs and larger FPGAs in the programmable logic hierarchy, offering deterministic, single-cycle propagation delays that make them ideal for address decoding, glue logic, bus arbitration, and high-speed control sequencing. The MAX 7000 family pioneered EEPROM-based CPLD architecture and remains popular in legacy industrial, telecom, and embedded designs. Key features of the EPM7160SLC84-10 include 64 macrocells per LAB-organized array, programmable power-saving mode per macrocell, JTAG-compliant boundary-scan test, and a 5V VCCINT/VCCIO core supply. The PLCC-84 package is socket-compatible with the JEDEC-standard 84-pin PLCC footprint, allowing easy prototyping and rework. Each I/O pin supports user-programmable slew-rate control and open-drain output options, simplifying multi-voltage bus interfacing. The MAX 7000S architecture uses a classic AND/OR plane with product-term macrocells. Each macrocell contains a programmable flip-flop, a product-term array, and a configurable I/O control block, enabling both combinatorial and registered logic with deterministic 10 ns tPD. The architecture also supports JTAG-based ISP that allows the device to be reconfigured on the PCB without UV erasure, distinguishing it from one-time-programmable (OTP) predecessors. Typical applications include 5V industrial control systems, telecom backplane glue logic, address decoding for microprocessor/microcontroller systems, bus arbitration in legacy PCI/ISA designs, and replacement of multiple discrete 74-series logic ICs. The wide 5V tolerance makes it ideal for retrofitting older designs where 3.3V FPGAs cannot interface directly. When designing with the EPM7160SLC84-10, observe the 5.0V VCC requirement and ensure monotonic supply ramp-up; insufficient rise time can prevent proper JTAG initialization. Use Altera's MAX+PLUS II or Quartus II design software for fitting, simulation, and bitstream generation.
EPM7160SLC84-10N - MAX 7000S CPLD 160 Macrocells 84-PLCC | Intel
The Intel (formerly Altera) EPM7160SLC84-10N is a member of the MAX 7000S family of high-density, high-performance CMOS Complex Programmable Logic Devices (CPLDs), delivering 160 macrocells, 3,200 usable gates, and 64 user I/O pins housed in an 84-pin Plastic Leaded Chip Carrier (PLCC) package with a -10 speed grade (10 ns pin-to-pin delay). The device operates from a 5.0 V core supply (VCC) with 3.3 V or 5.0 V tolerant I/O via the VCCIO pins, making it directly compatible with both 3.3 V and 5.0 V logic families. The -N suffix indicates this variant is the lead-free / RoHS-compliant commercial-grade offering. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that sits in the hierarchy between simple SPLDs/PLDs and large FPGAs. It belongs to the broader category of programmable logic devices -> logic ICs -> integrated circuits. CPLDs use EEPROM or flash-based configuration cells to retain their logic implementation without external boot memory, providing instant-on behavior that FPGAs cannot match, which is why they remain preferred for glue logic, bus interfacing, and state-machine control in cost-sensitive designs. The EPM7160SLC84-10N uses Altera's second-generation MAX architecture with 4 Logic Array Blocks (LABs), each containing 16 macrocells, plus a programmable interconnect array (PIA) for signal routing. The device features in-system programmability (ISP) via the built-in IEEE Std. 1149.1 JTAG interface, allowing board-level reconfiguration without removing the device. Counter speeds reach up to 175.4 MHz and the EEPROM-based configuration memory supports 100 program/erase cycles, retaining logic for at least 20 years. This device is widely deployed in legacy industrial control, telecommunications glue logic, address decoding, peripheral interfacing, and bus-bridging applications. It is particularly attractive for designs that need deterministic pin-to-pin timing (10 ns) and instant-on non-volatile configuration. The 5V core with multi-voltage I/O is favored in factory automation and military/aerospace subsystems where 5V tolerance is mandatory. When designing with the EPM7160SLC84-10N, allocate the global clear (GCLRn), global clock (CLK1/3), and OE pins carefully because these dedicated pins cannot be repurposed as general I/O. Use the Altera MAX+PLUS II or Quartus II design software for synthesis, fitting, and JTAG programming. Decouple VCC and VCCIO pins with 0.1 uF ceramic capacitors placed as close to the package as possible. This page synthesizes distributor pricing, drop-in same-package alternatives (same-family MAX 7000S speed grades), and practical design notes not found in the manufacturer datasheet alone.
EPM7160SLC84-15 - MAX 7000 CPLD, 160 Macrocells, 15ns | Altera
The Altera (now Intel) EPM7160SLC84-15 is a member of the classic MAX 7000 Complex Programmable Logic Device (CPLD) family, delivering 160 macrocells with a maximum pin-to-pin propagation delay of 15 ns. Housed in an 84-terminal Plastic Leaded Chip Carrier (PLCC-84 / PQCC84, JESD-30 code S-PQCC-J84) package with a 1.270 mm terminal pitch, the device operates from a nominal 5 V supply (4.75 V to 5.25 V) and supports configurable I/O operation at 3.3 V or 5 V. It is fabricated in CMOS technology with EEPROM configuration memory, providing non-volatile, in-system programmability through the standard JTAG (IEEE 1149.1) interface. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that bridges the gap between simple SPLDs/GALs and full FPGAs. It provides deterministic, single-fabrication-cycle pin-to-pin timing that is critical for glue-logic, bus decoding, and state-machine replacement. A CPLD such as the EPM7160SLC84-15 belongs to the broader programmable-logic family within digital semiconductors, sitting hierarchically between discrete logic gates (74-series) and high-density FPGAs in both density and architectural complexity. Key features include 160 logic macrocells, 3,200 usable gates, a 15 ns maximum propagation delay, and 64 user I/O pins routed through the 84-pin PLCC package. The MAX 7000 architecture uses a classic AND/OR plane connected via a programmable interconnect array to a bank of macrocells, each containing a programmable flip-flop, product-term allocation, and I/O control block. The EPM7160SLC84-15 is the -15 speed grade variant of the EPM7160 series, with faster grades (-7, -10) and the EPM7160E 5 V-tolerant enhanced version also available in the same PLCC-84 package. Typical applications include industrial control glue logic, telecommunications infrastructure bus interfaces, address decoding for legacy microprocessors and DSPs, I/O expansion through register replacement, and consumer electronics peripheral controllers. The device's deterministic timing, zero-power non-volatile configuration, and high-drive 5 V tolerant I/O also make it suitable for prototyping and low-volume production runs where the design may need frequent in-system updates. When designing with this device, ensure a robust 5 V decoupling network of 0.1 uF and 10 uF capacitors within 1 cm of each VCC/ground pair. Because the MAX 7000 is non-volatile, the JTAG ISP interface (TCK/TMS/TDI/TDO plus the ENABLE pin) should be brought to a 2.54 mm header or test pad to allow field re-programming. Operating temperature is restricted to 0 C to 70 C in the commercial grade - the -15 speed grade is not available with industrial-temperature screening. This page synthesizes distributor pricing, drop-in PLCC-84 alternatives from the same MAX 7000 family, and practical CPLD design notes not found in a single manufacturer document.
EPM7160SLC84-6 - MAX 7000S CPLD 160 Macro 6ns 84-PLCC | Intel
The Intel (formerly Altera) EPM7160SLC84-6 is a high-performance, EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000S family, featuring 160 macrocells, 3.2K usable gates, 64 user I/O pins, and a 6 ns pin-to-pin logic delay, housed in an 84-pin Plastic Leaded Chip Carrier (PLCC) package. It operates from a single 5.0 V supply (4.75 V to 5.25 V) and supports 5.0 V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-style macrocell arrays with a central interconnect matrix. CPLDs sit in the programmable logic hierarchy between simple SPLDs and higher-density FPGAs, offering deterministic timing, instant-on configuration from on-chip EEPROM, and superior pin-to-pin delay consistency. The MAX 7000S family specifically targets glue-logic, bus interfacing, and state-machine applications where predictable timing matters more than raw gate count. Key features include 4 Logic Array Blocks (LABs) of 16 macrocells each, 36 usable I/O pins with MultiVolt I/O supporting mixed-voltage interfacing, and a 149.3 MHz internal counter frequency. The device is built on a CMOS EEPROM process, providing reprogrammability without external configuration memory. The -6 speed grade denotes the 6 ns tPD timing bin, the fastest standard speed grade offered in the MAX 7000S family for the EPM7160 density tier. The EPM7160SLC84-6 uses a second-generation MAX architecture with a programmable interconnect array (PIA) that routes signals between LABs. Every macrocell contains a programmable flip-flop, product-term logic, and a configurable I/O control block. JTAG boundary-scan test (BST) circuitry conforms to IEEE 1149.1, enabling board-level test access without bed-of-nails fixtures. The on-chip EEPROM cells retain configuration indefinitely without a battery. Typical applications include bus-interface bridging (PCI, ISA, VME), peripheral glue logic in microcontroller and microprocessor systems, state-machine controllers, address decoding and wait-state generation, and 5 V logic integration in industrial control and legacy computing equipment. The deterministic timing also suits telecommunications backplane glue, motor-control sequencing, and military/aerospace subsystems requiring instant-on behavior. When designing with this device, plan for 5 V-tolerant inputs with MultiVolt outputs and note that JTAG programming requires a 1149.1-compliant header. The 84-PLCC package is socket-friendly for prototyping and field upgrades, but engineers should evaluate the newer MAX II or MAX V families for new designs, since MAX 7000S is an older legacy family. This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes not found in the original 1998-vintage datasheet, providing an engineer-ready reference for sourcing decisions on legacy Altera/Intel CPLD designs.
EPM7160SLI84-10 - MAX 7000S CPLD, 160 Macrocells, 84-PLCC | Intel
The Intel (formerly Altera) EPM7160SLI84-10 is a high-performance Complex Programmable Logic Device (CPLD) from the MAX 7000S family, integrating 3,200 usable gates and 160 macrocells in an 84-pin Plastic Leaded Chip Carrier (PLCC) package. It is built on a 5.0-V CMOS process and offers a 10 ns pin-to-pin propagation delay with an internal counter frequency up to 167 MHz. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that sits between simple PLDs/gate arrays and full FPGAs in the programmable logic hierarchy. CPLDs provide fast, deterministic input-to-output combinational and registered logic, instant-on behavior from on-chip EEPROM configuration memory, and typically tens to hundreds of macrocells organized into Logic Array Blocks (LABs). The MAX 7000S family from Intel/Altera represents a second-generation MAX architecture widely used for address decoding, glue logic, bus interfacing, and state-machine control in 5V systems. Key features of the EPM7160SLI84-10 include 64 user I/O pins, MultiVolt I/O support for interfacing with 2.5V/3.3V/5V systems, in-system programmability via IEEE Std. 1149.1 (JTAG) interface, programmable speed/power optimization per macrocell, and 5.0-V ISP through dedicated JTAG pins. The device operates over a commercial 0C to +70C temperature range. Architecturally, the EPM7160SLI84-10 implements 160 macrocells grouped into Logic Array Blocks (LABs), each containing 16 macrocells with a shared programmable interconnect array (PIA). The EEPROM-based configuration cell enables instant-on operation at power-up with no external boot PROM, a key advantage over SRAM-based FPGAs in industrial control applications. The 10 ns tpd supports high-speed bus decoding at frequencies approaching 100 MHz. Typical applications include 5V TTL/CMOS bus decoding and address mapping, peripheral glue logic in microprocessorbased systems, state-machine controllers for industrial automation, JTAG-programmed prototype logic, and I/O expansion for legacy industrial controllers. The 84-PLCC package provides robust through-hole or socket-mounting for harsh industrial environments. Designers should note that the EPM7160SLI84-10 is in the MAX 7000S family (commercial temperature grade); for industrial-temperature applications requiring 40C to +85C, the EPM7160SRI84-10 variant must be selected. The 'S' suffix indicates the enhanced MAX 7000S series with MultiVolt I/O and ISP; the 'L' denotes low-power architecture. This page aggregates distributor pricing, pin-compatible MAX 7000S alternatives, and design guidance not consolidated in the original 1998-vintage datasheet, supporting both legacy maintenance and new 5V-system designs.
EPM7160SQC160-10 - MAX 7000S CPLD, 160 Macro Cells, 100MHz, PQFP-160 | Intel / Altera
The Intel / Altera EPM7160SQC160-10 is a high-density, EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000S family, featuring 160 macro cells, 3,200 usable gates, and 104 user I/O pins housed in a 160-pin PQFP package. It supports in-system programmability (ISP) via a 5.0V JTAG-compatible interface and is built on Altera's second-generation MAX architecture with CMOS technology. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like logic blocks with a programmable interconnect matrix, sitting in the broader taxonomy of programmable logic -> logic devices -> digital ICs -> semiconductors. CPLDs are valued for deterministic pin-to-pin propagation delay (typically 5-10 ns), instant-on configuration from non-volatile EEPROM, and the ability to replace dozens of discrete 74-series glue-logic chips on a board. Key features of the EPM7160SQC160-10 include 160 macro cells organized in 10 Logic Array Blocks (LABs), a 100 MHz internal operating frequency, 6 ns pin-to-pin propagation delay (tPD), and 5.0V in-system programmability through the IEEE 1149.1 (JTAG) boundary-scan interface. The 104 user I/Os support 5V tolerant inputs with 3.3V or 5V output options, and the device offers programmable power-saving modes that reduce standby current. The MAX 7000S architecture uses an EEPROM cell array that holds configuration even when power is removed, eliminating the need for external boot PROMs. Each macro cell contains a programmable AND/OR array and a configurable flip-flop, allowing designers to implement both combinatorial and registered logic at deterministic timing. The interconnect is a continuous, fast path between LABs, with predictable propagation delay that simplifies static-timing closure. Typical applications include bus-interface glue logic for microprocessor and DSP systems, peripheral controllers in industrial automation, state-machine implementation in legacy 5V designs, and address decoding for memory subsystems. The wide 5V I/O tolerance makes the part especially useful as a bridge between modern 3.3V controllers and legacy 5V peripherals. When designing with this device, observe that propagation delay is specified at 10 ns (the "-10" speed grade) and that supply voltage is 5V; substituting it into a 3.3V-only board will not function. The JTAG chain must be designed to allow ISP re-programming without removing the part from the board, and unused I/O pins should be left floating or terminated per the datasheet to minimize quiescent current. This page synthesizes distributor pricing, drop-in alternative CPLDs in the same PQFP-160 footprint, and practical design notes not found in the manufacturer datasheet, providing a single engineering reference for sourcing, replacement, and circuit integration decisions.
EPM7160SQC160-10N - 160 Macrocells MAX 7000S CPLD, 10ns, PQFP-160
The Intel (formerly Altera) EPM7160SQC160-10N is a high-density, EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000S family, offering 160 macrocells, 3,200 usable gates, and a 10 ns pin-to-pin delay in a 160-pin PQFP (Plastic Quad Flat Pack) package. It features an internal counter frequency of up to 167 MHz and 104 user I/O pins, making it suitable for high-performance glue-logic, bus interfacing, and state-machine applications in industrial and legacy systems. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell arrays on a single chip with a programmable interconnect matrix. Positioned in the taxonomy as programmable logic -> PLD -> CPLD -> MAX 7000S family, the EPM7160SQC160-10N sits between simple PAL/GAL devices and larger FPGAs, offering instant-on EEPROM technology, deterministic timing, and 5V tolerant I/O. The MAX 7000S series uses Altera's second-generation MAX architecture with the Classic IEEE Std 1149.1 JTAG interface for in-system programming (ISP). Key features include 3,200 usable gates, 160 macrocells, 10 ns tPD (pin-to-pin delay), 167 MHz maximum internal frequency, 5.0V VCCINT, in-system programmability via JTAG, and open-drain / programmable I/O standards. The architecture provides four dedicated inputs per macrocell, a global clock network, and a programmable power-saving mode that reduces standby current by up to 50 percent when the device is idle. Typical applications include bus decoding and address mapping in 5V legacy systems, glue-logic replacement for multiple discrete TTL/CMOS gates, peripheral controllers (UART, FIFO, DMA), state machines for motor control front-ends, and I/O expansion in 8051/MCS-51 embedded designs. The 160-pin PQFP package provides ample I/O for wide data buses and parallel interfaces. This page synthesizes distributor pricing (as of 2026-09-13), drop-in MAX 7000S alternatives, and practical design notes for the EPM7160SQC160-10N that are not aggregated on any single manufacturer or distributor page.
EPM7160SQC160-6 - 160-Macrocell MAX 7000S CPLD, 6ns, PQFP-160 | Altera
The Altera (Intel) EPM7160SQC160-6 is a high-density, EEPROM-based, in-system programmable Complex Programmable Logic Device (CPLD) from the MAX 7000S family, delivering 160 macrocells, 3,200 usable gates, and 104 user I/Os in a 160-pin PQFP (Plastic Quad Flat Pack) package. The device operates from a 5 V supply (4.75 V to 5.25 V), provides a 6 ns pin-to-pin propagation delay, and supports a maximum internal frequency of 167 MHz, making it suitable for high-performance glue-logic, bus interfacing, and state-machine applications. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL/GAL-like macrocell blocks on a single die with a centralized interconnect matrix. Architecturally, a CPLD sits between small SPLDs/GALs and large FPGAs: it offers deterministic timing (fixed, predictable propagation delay), instant-on behavior (no external boot ROM required), and high-drive I/O cells optimized for bus bridging and I/O expansion. The MAX 7000S family is built on a second-generation MAX architecture using EEPROM configuration cells, which provides true in-system programmability (ISP) via JTAG. Key features of the EPM7160SQC160-6 include four dedicated input pins that operate as global clock, clear, output enable, and preset network signals; ten Logic Array Blocks (LABs) each containing 16 macrocells; programmable interconnect array (PIA) routing; user-programmable macrocell flip-flops with individually programmable clock, clear, preset, and enable controls; per-pin slew-rate control for EMI-sensitive designs; and a JTAG-compliant boundary-scan interface (IEEE Std 1149.1). The 5.0 V ISP allows designers to reconfigure the device on the board without removing the part. The EEPROM process technology gives the EPM7160SQC160-6 non-volatile configuration retention (no external configuration memory needed) and 100 program/erase cycles endurance. Each macrocell implements a sum-of-products logic expression with a programmable flip-flop that can be configured as D, T, JK, or SR. The interconnect architecture delivers fixed, deterministic timing paths with predictable setup/hold — an advantage over SRAM-based FPGAs in latency-sensitive control applications. Typical applications include 32-bit/16-bit peripheral bus interfacing (PCI, ISA, VME), address decoding and chip-select generation for microprocessors, glue logic between microcontrollers and memory devices, state-machine control for industrial automation, high-speed bus arbitration, and I/O expansion for legacy designs. The 6 ns propagation delay and 167 MHz internal frequency are sufficient for 50 MHz synchronous bus cycles with comfortable margin. When designing with the EPM7160SQC160-6, designers should note the 160-pin PQFP package is pin-compatible with other MAX 7000S members in the same package, which simplifies migration between 7128/7160/7192 densities. The 5 V supply simplifies interface to TTL/CMOS peripherals but limits use in modern 3.3 V-only systems without level translation. The device is specified for commercial temperature range (0°C to 70°C). This page synthesizes distributor pricing, drop-in alternatives from the same MAX 7000S family, and practical design notes that are not aggregated in the original Altera datasheet, helping engineers evaluate longevity, footprint compatibility, and migration paths.
EPM7160SQC160-7 - 160-Macrocell MAX 7000S CPLD, 7.5ns | Altera
The Altera EPM7160SQC160-7 is a 160-macrocell high-density CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000S family, housed in a 160-pin Plastic Quad Flat Pack (PQFP/BQFP) surface-mount package and specified at the -7 speed grade with 7.5 ns maximum pin-to-pin propagation delay. The device integrates 3,200 usable system gates across 10 Logic Array Blocks (LABs) and 160 macrocells, each containing a programmable AND/OR array with 32 product terms, supporting fast and predictable combinational and registered logic implementation. The 'S' suffix indicates in-system programmability (ISP) through a built-in IEEE 1149.1 JTAG interface operating from a single 5.0 V supply (4.75 V to 5.25 V), which allows board-level reconfiguration without removing the device. A CPLD is a non-volatile programmable logic device that combines multiple PAL-like macrocells on a single chip with on-chip EEPROM configuration memory, providing instant-on behavior at power-up with no external boot PROM. The MAX 7000S architecture belongs to the broader programmable logic family, sitting between small SPLDs/GALs and larger FPGAs; it excels at glue-logic, bus interfacing, address decoding, and state-machine replacement where deterministic timing and 5 V tolerance are required. The part is commercial-grade (0 °C to 70 °C) and its output drivers can be configured for 3.3 V or 5.0 V operation, enabling mixed-voltage system designs. Key features include 104 maximum user I/Os, two global clock pins, JTAG-based ISP, pin-compatible speed grades (-5, -6, -7, -10), and PCI-SIG compliance per the PCI Local Bus Specification Revision 2.2. The high pin count makes it suitable for byte-wide bus bridging and address/data demultiplexing. The device is fully supported by Altera's legacy MAX+PLUS II and Quartus II design tools, with the latter providing modern Verilog/VHDL and schematic entry. Typical applications include PCI bus interface glue logic, peripheral controller glue logic between microprocessors and memory, address decoding and chip-select generation, bus-width translation between 5 V and 3.3 V domains, and replacement of multiple discrete 22V10 / GAL devices. The instant-on, non-volatile configuration also suits industrial control and instrumentation boards where deterministic boot behavior is required. When designing with this part, observe the I/O banking rules for 3.3 V versus 5.0 V outputs and provide adequate decoupling (one 0.1 µF per VCC/GND pair plus a bulk 10 µF). For JTAG ISP, ensure TMS, TDI, TDO, and TCK are routed with short traces and the TRST pin is handled per datasheet guidance. Choose the -6 or -10 speed grade if 7.5 ns is over-budget for the timing closure target.
EPM7160STC100-10 - MAX 7000S CPLD, 160 Macrocells, 100-pin TQFP | Intel
The Intel (formerly Altera) EPM7160STC100-10 is a high-density, high-performance EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000S family, featuring 160 macrocells, 84 user I/Os, and 3.2K usable gates in a 100-pin TQFP package with a 10 ns pin-to-pin propagation delay and 5.0 V operation. The device is fabricated in advanced CMOS technology and supports in-system programmability (ISP) through the IEEE Std. 1149.1 JTAG interface, allowing field upgrades without removing the part from the board. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell arrays on a single chip with a programmable interconnect matrix. In the system hierarchy, a CPLD sits between simple SPLDs (PALs/GALs) and larger FPGAs, offering deterministic timing, instant-on behavior from non-volatile EEPROM, and typically lower I/O counts than FPGAs but higher logic density than 22V10-style GALs. The MAX 7000S family is Altera's second-generation MAX architecture, characterized by fast 5-10 ns propagation delays and pin-compatible upgrades within the family. Key features of the EPM7160STC100-10 include 160 macrocells organized in logic array blocks (LABs), 84 user I/Os, 3.2K usable gates, a 100 MHz internal counter frequency, and 5.0 V VCC operation. The -10 speed grade denotes a 10 ns maximum pin-to-pin delay (tPD1) and a 6 ns global clock setup time, suitable for glue-logic, bus-interface, and state-machine applications where deterministic timing is critical. The device also offers programmable power savings with 50% or 100% toggle-rate reduction modes, multi-voltage I/O support, and JTAG boundary-scan test compliance. Architecturally, the EPM7160STC100-10 uses an EEPROM cell to store the configuration, which means the device powers up instantly in a known state without external boot memory. Each macrocell contains a programmable AND/OR array, a product-term allocator, a flip-flop, and an I/O control block, providing both combinational and registered logic with flexible feedback paths. The interconnect uses Altera's FastTrack continuous interconnect matrix, minimizing routing delay variations across the chip. Typical applications include bus-interface bridging (e.g., 8-bit/16-bit MCU to 32-bit peripheral glue-logic), address decoding and chip-select generation in microprocessor systems, state-machine control for industrial automation, peripheral interface adaptation (UART, SPI, I2C, parallel buses), and legacy TTL/CMOS logic integration on a single programmable device. The instant-on EEPROM configuration also suits safety-critical and automotive underhood applications requiring deterministic power-up behavior. Designers should note that the EPM7160STC100-10 belongs to a mature, multi-decade product family; some speed grades and temperature grades have been migrated to the -10N suffix variant. For new designs, evaluate MAX II or MAX V CPLDs as modern equivalents, but for pin-compatible drop-in replacement on existing PCBs the EPM7160STC100-10N, EPM7160STC100-7, and EPM7160STC100-15 offer parametric-equivalent second sources within the same 100-pin TQFP footprint. This page synthesizes distributor pricing, JTAG/ISP programming parameters, and same-family drop-in alternatives not found in a single distributor listing, with values anchored to the manufacturer datasheet and DigiKey/Mouser inventory data as of 2026-09-13.
EPM7160STC100-10F - 160-Macrocell MAX 7000S CPLD, 10ns, TQFP-100
The Intel (formerly Altera) EPM7160STC100-10F is a high-density, high-performance Complex Programmable Logic Device (CPLD) from the MAX 7000S family, delivering 160 macrocells, 3,200 usable gates, and 100 MHz pin-to-pin performance in a 100-pin TQFP (1.0 mm height, lead-free) package with a 10 ns propagation delay. Built on a 5 V CMOS process, this non-volatile EEPROM-based device provides in-system programmability via IEEE Std. 1149.1 (JTAG) and supports the SameFrame pin-out migration strategy that allows multiple MAX 7000S densities to share a common PCB layout. A CPLD (Complex Programmable Logic Device) is a non-volatile, flash/EEPROM-backed programmable logic device that combines the deterministic timing of PAL/GAL architecture with higher logic density, multi-level macrocell arrays, and on-chip programmable interconnect. CPLDs sit between discrete logic ICs (74-series gates) and FPGAs in the programmable logic hierarchy: FPGAs offer higher density and richer features but require external boot memory and have unpredictable timing; CPLDs boot instantly from on-chip non-volatile memory and deliver predictable pin-to-pin delays of a few nanoseconds. The MAX 7000S family is the second-generation MAX architecture, optimized for 5 V system designs requiring glue logic, bus decoding, state-machine control, and high-speed interface bridging. Key features include 84 user I/O pins (5 V tolerant), four dedicated inputs, programmable power-saving mode per macrocell, programmable security bit for design protection, in-system programmability through the JTAG interface, and a multi-volt I/O interface that allows mixed-voltage operation with 5.0 V, 3.3 V, and 2.5 V devices on the same board. The 10 ns pin-to-pin delay translates to approximately 100 MHz system frequency on combinatorial paths, sufficient for fast state-machine and address-decoding tasks. Typical applications include bus-interface bridging (PCI, ISA, VME), address decoding and chip-select generation, high-speed glue logic replacement for 74-series TTL/CMOS gates, state-machine controllers, and 5 V industrial control systems that need non-volatile, instant-on programmable logic. The SameFrame pin-out enables migration across MAX 7000S variants (EPM7128S, EPM7160S, EPM7192S, EPM7256S) on the same 100-pin TQFP footprint, allowing designers to swap densities without PCB rework. When designing with this device, ensure the JTAG chain is correctly terminated with the TCK, TMS, TDI, and TDO pins accessible for ISP. Use Altera/Intel Quartus II (or legacy MAX+PLUS II) for design entry, fitting, and programming; the device supports both 4-pin JTAG and ByteBlaster programming modes. Verify that the 5 V supply is well-decoupled with 100 nF + 10 µF capacitors near the VCC pins. This page synthesizes distributor pricing, drop-in MAX 7000S SameFrame alternatives, and practical design notes not found in the manufacturer datasheet alone.
EPM7160STC100-10N - MAX 7000 CPLD, 160 Macrocells, TQFP-100 | Altera
The Altera (now Intel) EPM7160STC100-10N is a member of the MAX 7000S family of high-density, high-performance CMOS EEPROM-based complex programmable logic devices (CPLDs), delivering 160 macrocells, 84 user I/Os, and a 10 ns pin-to-pin propagation delay in a 100-pin TQFP package. A CPLD (Complex Programmable Logic Device) is a non-volatile, reprogrammable digital integrated circuit that combines multiple PAL/GAL-like logic blocks on a single chip with a central interconnect matrix. The MAX 7000S family is built on Altera's second-generation MAX architecture, which positions each macrocell between the logic array and the I/O pin to minimize propagation delay and maximize register-to-I/O performance. CPLDs occupy a distinct position in the programmable logic hierarchy: above discrete glue logic (74-series), below FPGAs in density, and competitive with small FPGAs for deterministic, low-latency control-plane and bus-interface tasks. Key features of the EPM7160STC100-10N include 3.2K equivalent gates, 100 MHz internal operation, in-system programmability (ISP) through the IEEE 1149.1 JTAG interface, 5.0 V VCCIO compatibility with 3.3 V and 5.0 V systems, and MultiVolt I/O that allows mixed-voltage interfacing. The -10 speed grade denotes a 10 ns tPD maximum, suitable for 66 MHz PCI bus interfaces and high-speed glue-logic replacement. Per the verified chip-source summary, the device offers an internal frequency of 167 MHz and 64 user I/Os within a plastic LCC-84 footprint variant context; the -10N TQFP-100 variant aligns with the broader MAX 7000S pinout family. The architecture combines four Logic Array Blocks (LABs) connected through a Programmable Interconnect Array (PIA), with each macrocell containing a programmable AND/OR array, a flip-flop, and routing to global or local control signals. The EEPROM configuration cell is non-volatile, allowing instant-on behavior at power-up with no external boot PROM. ISP via JTAG enables field upgrades without removing the device from the board. Typical applications include PCI bus interface bridging, address decoding and glue-logic replacement, peripheral adapters, and 5 V/3.3 V mixed-voltage system controllers. The wide operating temperature (commercial 0C to 70C) and the legacy MAX 7000S family heritage make it a drop-in solution for industrial and embedded designs that have long service-life requirements. When designing with this part, route JTAG signals TMS, TCK, TDI, TDO through dedicated test access pins and provide a clean 5 V supply with adequate decoupling. Verify pin compatibility with the specific TQFP-100 footprint revision on your PCB before committing to layout, since the MAX 7000S family includes several die/package variants with different I/O counts and ball/pin assignments. This page synthesizes distributor pricing, drop-in alternatives, and design notes not found in the manufacturer datasheet alone.
EPM7160STC100-6N - 160-Macro MAX 7000S CPLD, 6ns TQFP-100 | Altera
The Altera (Intel) EPM7160STC100-6N is a high-performance, EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000S family, featuring 160 macro cells, 84 user I/Os, and a 6 ns pin-to-pin propagation delay. Housed in a 100-pin TQFP (T100) package, this device operates from a 5V supply and supports in-system programmability (ISP) through the IEEE 1149.1 JTAG interface. The '-6N' suffix denotes the commercial temperature grade (0°C to +70°C) and the 6 ns speed grade. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macro-cell arrays with a central interconnect matrix. CPLDs sit in the broader programmable logic hierarchy: CPLD -> PLD -> programmable logic -> digital semiconductor -> integrated circuit. Compared to FPGAs, CPLDs offer deterministic timing, instant-on from non-volatile EEPROM, and lower power consumption for glue-logic and control-plane applications, making them ideal for bus interfacing, state-machine decoding, and I/O expansion. The EPM7160STC100-6N delivers up to 149.3 MHz internal frequency and approximately 3,200 usable gates. Key features include 5.0V in-system programmability, JTAG boundary-scan support per IEEE Std 1149.1, programmable power management to reduce standby current, and a programmable macrocell flip-flop with clock-enable, clear, and preset controls. The TQFP-100 package exposes 84 usable I/O pins with 3.3V or 5V I/O capability. Built on a CMOS EEPROM process with second-generation MAX architecture, the device provides predictable timing with 4 ns global propagation delay and a fixed-pin architecture that simplifies PCB design. Multiple I/O banks support mixed-voltage interfacing, and the JTAG port enables post-assembly reconfiguration without removing the part from the board. Typical applications include bus-interface bridging (e.g., address decoding for legacy microcontrollers), peripheral glue logic, power-sequencer controllers, and interface translation between 5V and 3.3V logic domains. Industrial and consumer control boards commonly use this part for deterministic state-machine implementation. When designing with this part, allocate JTAG pins (TDI, TDO, TMS, TCK) early in the schematic, because reassigning them mid-layout complicates the JTAG chain. The device is non-volatile, so configuration loads instantly on power-up, eliminating the boot-time delay common to FPGAs. This page synthesizes distributor pricing, same-family drop-in alternatives, and JTAG layout guidance not found in the standalone datasheet.
EPM7160STI100-10 - MAX 7000S CPLD, 160 Macrocells, 100MHz | Altera
The Altera (Intel) EPM7160STI100-10 is a high-density, high-performance EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000S family, featuring 160 macrocells, 84 user I/Os, and a 10ns pin-to-pin propagation delay, housed in a 100-pin TQFP package with industrial temperature grade. A CPLD (Complex Programmable Logic Device) is a non-volatile, flash- or EEPROM-based programmable logic device that combines multiple PAL/GAL-like macrocell arrays with a central interconnect matrix. The MAX 7000S family is built on Altera's second-generation MAX architecture with 5.0V in-system programmability (ISP), pin compatibility with the original 5.0V MAX 7000S family, and PCI Local Bus Specification Revision 2.2 compliance for the -10 speed grade. CPLDs occupy the middle ground between simple SPLDs and high-density FPGAs, delivering deterministic timing, instant-on non-volatile configuration, and high I/O count at lower cost-per-logic-block. Key features include 3,200 usable gates, 160 macrocells, 84 user I/Os, 10ns tPD propagation delay, 100MHz maximum operating frequency, and an internal 4.75V to 5.25V supply with 5.0V-tolerant I/O. The device supports JTAG-based IEEE Std. 1149.1 boundary-scan testing and in-system programmability through the JTAG interface, eliminating the need for external programmers. The TQFP-100 surface-mount package provides a compact footprint for space-constrained designs, while the industrial -40C to +85C temperature range (denoted by the 'I' suffix) supports harsh-environment deployment. The EPM7160STI100-10 employs Altera's classic EEPROM cell technology, retaining configuration across power cycles without external boot memory. Its deterministic routing fabric and predictable 10ns delay make it suitable for glue logic, bus interface bridging, and state-machine implementation where timing predictability is critical. The 84 available I/Os support wide bus interfaces and parallel peripheral control. Typical applications include PCI bus interface logic, microprocessor peripheral glue logic, bus arbitration and address decoding, state-machine control in industrial automation, and high-density TTL/CMOS logic integration. The 5V core supply and 5V-tolerant I/Os align with legacy industrial and telecom infrastructure that has not yet migrated to 3.3V. When designing with this device, plan the JTAG chain with proper TCK/TMS/TDI/TDO pull-ups and ensure the VCCIO rail matches the connected logic level. Note that the -10 speed grade supports PCI 2.2 timing. This page synthesizes distributor pricing, drop-in MAX 7000S alternatives, and practical design notes not found in the manufacturer datasheet alone.
EPM7160STI100-10N - MAX 7000S CPLD, 160 Macrocells, 100MHz, TQFP-100 | Intel/Altera
The Intel (formerly Altera) EPM7160STI100-10N is a high-density, high-performance EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000S family, packaged in a 100-pin TQFP and offering 160 macrocells, 84 user I/Os, and a 10 ns pin-to-pin propagation delay. Built on Altera's second-generation MAX architecture with 3.2K usable gates and 5.0V in-system programmability (ISP), this device targets glue-logic, interface bridging, and bus-decoding applications in industrial and commercial designs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the instant-on characteristics of PAL/GAL architectures with the high integration density of FPGAs. Within the broader taxonomy, a CPLD is a sub-category of programmable logic devices (PLDs), sitting above discrete 22V10 GALs in density and below modern low-power FPGAs. The MAX 7000S family sits in Altera's classic mid-density CPLD portfolio and is widely used as the 'glue logic' layer between processors, memories, and peripherals in 5V-tolerant systems. Key differentiating features include a 5.0V core and I/O supply, 3.3V or 5V multi-voltage JTAG-based in-system programmability, 100 MHz internal performance, support for up to 84 user I/Os (some sources cite 104 I/Os for the TQFP-100 variant), and an industrial operating temperature range of -40C to +85C indicated by the 'I' suffix. The 'I' designator additionally implies lead-free assembly, an important differentiator versus the older non-I commercial variant. Architecturally, the EPM7160S pairs EEPROM configuration cells with a Logic Array Block (LAB) interconnect fabric, with macrocells combining programmable AND/OR arrays with configurable flip-flops. The MAX 7000S device supports JTAG-compliant IEEE 1149.1 boundary-scan testing, four user I/O pinout schemes via dedicated pin compatibility with other MAX 7000S density points, and a high-performance input path with a global clock network. Typical applications include address decoding and bus interface bridging in 5V microprocessor systems, peripheral glue-logic replacement for legacy 74-series TTL/CMOS logic, industrial control and instrumentation I/O expansion, power-supply sequencing logic, and JTAG-controlled in-system programmable front-ends. Designers frequently choose the EPM7160STI100-10N as a drop-in for end-of-life 22V10 and similar discrete PLD footprints. When designing with this part, pay particular attention to the 5.0V VCC requirement - the S-suffix variant uses 3.3V core, while the EPM7160S family generally operates at 5V - and ensure the JTAG chain respects IEEE 1149.1 ordering when multiple devices share the same boundary-scan test access port. This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet, with all data sourced from DigiKey, Mouser, Octopart and Altera/Intel device documentation.
EPM7192EGC160-12 - 192-Macrocell MAX 7000 CPLD, 12ns, 160-PGA | Intel
The Intel / Altera EPM7192EGC160-12 is a 192-macrocell, 124-I/O CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000 family, housed in a 160-pin Ceramic Pin Grid Array (CPGA / PGA-160) package with a 12 ns pin-to-pin propagation delay and 5.0 V core supply. The 'E' suffix denotes the enhanced MAX 7000E architecture with in-system programmability (ISP) via the built-in IEEE Std. 1149.1 JTAG interface, and 'GC160' identifies the ceramic pin-grid-array package. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on programmable logic device built from multiple PAL-like logic array blocks (LABs) joined by a central interconnect matrix. CPLDs sit hierarchically above simple PLDs (PAL/GAL) and below FPGAs, offering deterministic timing, fast I/O, and instant-on behavior with no configuration memory load time. They are widely used as glue logic, bus interfaces, and state-machine controllers. Key features of the EPM7192EGC160-12 include 192 macrocells across 4 logic array blocks (LABs) with 3.75K usable gates, 124 user I/O pins, 12 ns tPD propagation delay, and a 76.9 MHz maximum operating frequency per the manufacturer datasheet. The device operates from a single 5.0 V supply (4.75 V to 5.25 V) and supports 5.0 V in-system programmability through the JTAG-compliant IEEE 1149.1 boundary-scan test (BST) interface. The MAX 7000 family supports PCI Local Bus Specification Revision 2.2 timing compatibility in -4 to -10 speed grades. The MAX 7000 architecture combines EEPROM configuration memory (non-volatile) with a classic product-term / macrocell structure, delivering zero standby power for the configuration and deterministic 12 ns combinational delay regardless of how the design routes through the interconnect. This makes the EPM7192EGC160-12 especially attractive for legacy industrial designs that need robust, repeatable timing rather than the absolute logic density of an FPGA. Typical applications include industrial glue logic and bus-interface bridging, telecom backplane control, PCI bus interface glue, address decoding and DMA control in legacy embedded systems, and motor-control I/O expansion. Designers also use the EPM7192E in production ASIC prototyping where instant-on, non-volatile behavior is required. A key design consideration is the 160-pin PGA footprint: although it shares a pin count with some MAX 7000 variants in PQFP packages, the ceramic PGA is socket-friendly and well-suited for legacy / through-hole backplane designs, but it requires a different PCB land pattern than the PQFP / TQFP / QFP variants of the same die. Designers migrating between package options should verify the footprint before reassigning the BOM. This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet.
EPM7192EGI160-20 - 192-Macrocell CPLD, 20ns, 160-PGA | Intel
The Intel EPM7192EGI160-20 is a high-performance, EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000 family, delivering 192 macrocells organized into 4 Logic Array Blocks with a maximum pin-to-pin delay of 20 ns and a maximum operating frequency of approximately 62.5 MHz at 5 V, housed in a 160-pin Ceramic Pin Grid Array (CPGA) package with industrial temperature grade. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-style macrocell blocks on a single die, providing deterministic, interconnect-rich logic replacement for dozens of SSI/MSI chips. Within the broader taxonomy, the EPM7192EGI160-20 belongs to: CPLD -> programmable logic device -> logic IC -> integrated circuit. MAX 7000 devices use second-generation, EEPROM-based architecture that retains the bitstream when power is removed, eliminating the need for external boot PROMs and enabling in-system programmability via the IEEE Std. 1149.1 JTAG interface. Key features include 192 macrocells, 36 user I/O pins, 4 dedicated inputs, in-system programmability (ISP) through JTAG, and 5.0 V core operation. The device provides predictable timing with fixed propagation delays, multi-voltage I/O support for 3.3 V and 5 V interfaces, and a programmable power-saving mode that reduces individual macrocell power when logic is idle, while an enhanced security bit protects user designs from unauthorized read-back. The MAX 7000 architecture implements each macrocell as a product-term array feeding a programmable register, with a shared programmable interconnect array (PIA) routing signals between LABs. The EEPROM process technology allows unlimited reconfiguration cycles via JTAG, supporting field upgrades and rapid prototyping. The 4-LAB organization enables wide logic integration for state machines, address decoding, and bus-interface glue logic. Typical applications include bus-interface bridging, address decoding and wait-state generation, glue logic replacement around microprocessors and DSPs, peripheral control in industrial systems, and rapid prototyping of glue logic on 5 V legacy boards. The wide-gate count and JTAG ISP make it suitable for production designs that need flexibility without an FPGA. When designing with this part, observe 5 V supply tolerance on inputs and use level shifters for 3.3 V logic interfaces; the JTAG chain can remain populated during in-circuit test for board-level diagnostics. Decouple the VCC pins with 0.1 uF ceramic capacitors placed close to the package, and consult the manufacturer datasheet for the full PGA pin assignment. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design guidance not found on a single manufacturer datasheet page, giving engineers a single reference for sourcing and implementing the EPM7192EGI160-20.
EPM7192EGM160-15 - MAX 7000 CPLD, 192 Macrocells, PGA-160 | Altera
The Altera (now Intel) EPM7192EGM160-15 is a high-density, high-performance CMOS EE PLD from the second-generation MAX 7000 family, providing 192 macrocells, 3750 usable gates, and 124 user I/O pins in a 160-pin PGA (Pin Grid Array) ceramic package. It operates with a 15 ns pin-to-pin logic delay and is supplied by a 5 V core with 3.3 V or 5 V configurable I/O banks for mixed-voltage interfacing. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-style macrocell arrays on a single die with a programmable interconnect fabric. CPLDs sit between simple SPLDs and FPGAs in the programmable logic hierarchy: they offer deterministic, instantly-on combinational and registered logic with hundreds to thousands of flip-flops, making them ideal for glue logic, bus interfacing, address decoding, and state-machine replacement. The MAX 7000 family is Altera's second-generation CPLD architecture and represents the industry's longest-shipped CPLD line. Key features of the EPM7192EGM160-15 include in-system programmability through Altera's ByteBlaster or BitBlaster interfaces via JTAG, 192 macrocells arranged in 12 Logic Array Blocks (LABs) of 16 macrocells each, four dedicated inputs per LAB, programmable interconnect with consistent delays, and per-macrocell registers configurable as D, T, JK, or SR flip-flops. Each macrocell offers configurable product-term allocation and a programmable power-saving mode. The device uses a 0.5 µm EEPROM-based process with 5 V tolerant I/O cells supporting 3.3 V PCI compliance when configured, and the ceramic PGA-160 package supports an industrial/military operating temperature range. The MAX architecture uses Altera's classic wired-AND AND-OR-INVERT (AOI) fabric with an expander product-term chain that efficiently implements wide gating functions. All MAX 7000E devices are 5 V core, 5 V tolerant I/O, and pin-compatible with the broader MAX 7000S family footprint in the same package option. Typical applications include address decoding for microprocessor/microcontroller systems, peripheral bus interfacing (ISA, PCI, VME), state-machine replacement in industrial control, glue logic for ASIC/FPGA-based designs, and high-reliability systems requiring non-volatile configuration. The ceramic PGA-160 package makes the EPM7192EGM160-15 particularly suited to military, aerospace, and industrial-temperature designs where plastic packages are not acceptable. When designing with this part, ensure 5 V ±5% supply regulation and provide proper JTAG chain termination. The PGA-160 ceramic socket should be specified for through-hole PCB assembly; SMD versions are available in the MAX 7000S QFP family if surface mount is required. This page synthesizes distributor stock, real-time pricing, MAX 7000 family alternatives, and practical CPLD design notes not found in a single source on the manufacturer datasheet.
EPM7192EGM160-20 - 192-Macrocell MAX 7000 CPLD, 20ns PGA-160 | Altera
The Altera (now Intel) EPM7192EGM160-20 is a 192-macrocell EE (electrically erasable) CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000 family, fabricated on a second-generation MAX architecture and housed in a 160-pin PGA package with 120 user I/O lines. It delivers 600 to 5,000 usable gates, in-system programmability (ISP) via IEEE Std. 1149.1 JTAG, pin-to-pin propagation delays as fast as 5 ns, and counter frequencies up to 175.4 MHz. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell arrays on a single chip with a programmable interconnect matrix. CPLDs sit in the programmable logic hierarchy between simple SPLDs (PALs/GALs) and high-density FPGAs, offering deterministic timing, instant-on behavior from on-chip EEPROM, and high drive capability - making them ideal for glue logic, bus interfacing, and state-machine replacement. As a member of the power-management-adjacent signal-conditioning category, the MAX 7000 family historically bridged discrete TTL logic and modern FPGAs in industrial, telecom, and military designs. Key features include 192 macrocells arranged in 12 Logic Array Blocks (LABs), 120 I/O pins with 3.3V/5V configurable I/O standards, two global clock inputs plus shared input/clock pins, programmable power saving per macrocell, and JTAG boundary-scan test per IEEE 1149.1. The -20 speed grade denotes a 20 ns pin-to-pin propagation delay. The EPM7192EGM160-20's electrically erasable EEPROM cell technology provides 100% tested 100 program/erase cycles and supports the JTAG-based In-System Programming (ISP) flow, eliminating the need for an external programmer. Combined with its industrial -40C to +125C operating range, the device targets long-lifecycle designs where design stability and reworkability matter more than absolute density. Typical applications include industrial control glue logic, telecom backplane bus interface bridging, legacy peripheral replacement for TTL/CMOS 74-series logic arrays, military and aerospace control electronics (under SMD 5962-93168), and JTAG-driven board-level test infrastructure. When designing with this part, ensure your ISP programming algorithm follows the MAX 7000 JTAG instruction set and that the global clock pins (GCLK1, GCLK2) and OE pins are assigned correctly to avoid contention. PGA-160 sockets are recommended over solder-mount to ease programming and rework. This page synthesizes distributor pricing across three channels, same-family drop-in alternates from the MAX 7000 family, and practical design notes for JTAG ISP not aggregated on the manufacturer datasheet.
EPM7192EQC160-20 - 192-Macrocell MAX 7000 CPLD, 20ns, PQFP-160 | Intel
The Intel (formerly Altera) EPM7192EQC160-20 is a 192-macrocell, 124-I/O EEPROM-based CPLD from the MAX 7000 family, housed in a 160-pin PQFP (28x28 mm) package with a 20 ns pin-to-pin propagation delay. It operates from a single 5.0 V supply (4.75 V to 5.25 V) and offers 5.0 V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. The device is organized as 4 Logic Array Blocks with 36 user I/O pins and supports JTAG boundary-scan testing per IEEE 1149.1. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell arrays on a single chip, providing deterministic timing, instant-on operation, and high-drive I/O for glue-logic, bus-interface, and state-machine applications. In the broader system hierarchy, the EPM7192EQC160-20 sits between small FPGAs and discrete logic ICs, offering instant-on behavior (no boot PROM required), predictable timing for register-rich designs, and 5 V tolerant I/Os that are increasingly rare in modern logic families. Key features include 192 macrocells distributed across 4 Logic Array Blocks, 36 I/O pins routed through programmable interconnect, programmable power-saving mode per macrocell, programmable security bit for design protection, and JTAG-based ISP that allows board-level reconfiguration without removing the device. The 20 ns speed grade provides a 50 MHz fCNT internal counter frequency and supports combinatorial and registered logic at typical 5 V system clocks. Architecturally, the MAX 7000 family uses second-generation MAX architecture with EEPROM process technology, providing non-volatile configuration storage that retains state through power cycles. The Programmable Interconnect Array (PIA) routes signals between LABs and I/O pins with predictable delays that simplify static-timing closure versus SRAM-based FPGAs. Each macrocell contains a programmable AND/OR array plus a configurable flip-flop that can be bypassed for pure combinatorial outputs. Typical applications include industrial control glue-logic, 5 V system bus interfacing, JTAG-controlled I/O expansion, address decoding for legacy microprocessor boards, and pin-compatible replacement for older MAX 7000 designs where instant-on, non-volatile configuration is required. The wide 5 V tolerance makes it especially attractive for industrial 5 V designs where 3.3 V-only modern CPLDs are unsuitable. When designing with this part, note that the PQFP-160 package requires fine-pitch PCB layout with controlled-impedance traces; place decoupling capacitors (0.1 uF and 10 uF) as close as possible to each VCC/GND pair, and use a JTAG header that meets IEEE 1149.1 specifications for in-system programming access. Verify the JTAG chain length and TCK pull-up/down values against the JTAG specification for reliable ISP operation.