EPM7160SQC160-7 - 160-Macrocell MAX 7000S CPLD, 7.5ns | Altera
부품 번호: EPM7160SQC160-7 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
EPM7160SQC160-7 개요
A CPLD is a non-volatile programmable logic device that combines multiple PAL-like macrocells on a single chip with on-chip EEPROM configuration memory, providing instant-on behavior at power-up with no external boot PROM. The MAX 7000S architecture belongs to the broader programmable logic family, sitting between small SPLDs/GALs and larger FPGAs; it excels at glue-logic, bus interfacing, address decoding, and state-machine replacement where deterministic timing and 5 V tolerance are required. The part is commercial-grade (0 °C to 70 °C) and its output drivers can be configured for 3.3 V or 5.0 V operation, enabling mixed-voltage system designs.
Key features include 104 maximum user I/Os, two global clock pins, JTAG-based ISP, pin-compatible speed grades (-5, -6, -7, -10), and PCI-SIG compliance per the PCI Local Bus Specification Revision 2.2. The high pin count makes it suitable for byte-wide bus bridging and address/data demultiplexing. The device is fully supported by Altera's legacy MAX+PLUS II and Quartus II design tools, with the latter providing modern Verilog/VHDL and schematic entry.
Typical applications include PCI bus interface glue logic, peripheral controller glue logic between microprocessors and memory, address decoding and chip-select generation, bus-width translation between 5 V and 3.3 V domains, and replacement of multiple discrete 22V10 / GAL devices. The instant-on, non-volatile configuration also suits industrial control and instrumentation boards where deterministic boot behavior is required.
When designing with this part, observe the I/O banking rules for 3.3 V versus 5.0 V outputs and provide adequate decoupling (one 0.1 µF per VCC/GND pair plus a bulk 10 µF). For JTAG ISP, ensure TMS, TDI, TDO, and TCK are routed with short traces and the TRST pin is handled per datasheet guidance. Choose the -6 or -10 speed grade if 7.5 ns is over-budget for the timing closure target.
드롭인 대체품: EPM7160SQC160-7 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EPM7160SQC160-7 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Operating Temperature, Supply Voltage (VCCINT), RoHS Status, Family.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EPM7160SQC160-6
✅ 드롭인✓ 재고 있음
$5.45 / 개
데이터시트 보기 →EPM7160SQC160-10
✅ 드롭인✓ 재고 있음
$12.2 / 개
데이터시트 보기 →EPM7160SQC160-10N
✅ 드롭인✓ 재고 있음
$8.1 / 개
데이터시트 보기 →EPM7160EQC160-12
✅ 드롭인✓ 재고 있음
$9.75 / 개
데이터시트 보기 →EPM7160SQC160-7
✅ 드롭인✓ 재고 있음
$9.75 / 개
데이터시트 보기 →EPM7160SQC160-7 최대 정격 & 전기적 특성
| Family | MAX 7000S |
| Macrocells | 160 |
| Logic Array Blocks (LABs) | 10 |
| Usable System Gates | 3,200 |
| Product Terms per Macrocell | 32 |
| Maximum User I/Os | 104 |
| Global Clocks | 2 |
| Speed Grade | -7 (7.5 ns pin-to-pin) |
| Maximum Propagation Delay (tPD) | 7.5 ns |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) |
| Program Memory Type | EEPROM (in-system programmable) |
| 동작 온도 | 0 °C to 70 °C (commercial) |
| 패키지 | 160-pin PQFP (BQFP, 28x28 mm) |
| 실장 유형 | Surface Mount |
| JTAG (IEEE 1149.1) | Yes (ISP via JTAG) |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 |
| RoHS 상태 | Not Compliant (per Arrow listing) |
| Part Status | Obsolete |
EPM7160SQC160-7 핀 구성
| 핀 1 | I/O — General-purpose user I/O (bank 1) |
| 핀 2 | I/O — General-purpose user I/O (bank 1) |
| 핀 3 | I/O — General-purpose user I/O (bank 1) |
| 핀 4 | I/O — General-purpose user I/O (bank 1) |
| 핀 5 | I/O — General-purpose user I/O (bank 1) |
| 핀 6 | I/O — General-purpose user I/O (bank 1) |
| 핀 7 | I/O — General-purpose user I/O (bank 1) |
| 핀 8 | I/O — General-purpose user I/O (bank 1) |
| 핀 9 | I/O — General-purpose user I/O (bank 1) |
| 핀 10 | I/O — General-purpose user I/O (bank 1) |
| 핀 11 | GND — Ground |
| 핀 12 | I/O — General-purpose user I/O (bank 1) |
| 핀 13 | I/O — General-purpose user I/O (bank 1) |
| 핀 14 | I/O — General-purpose user I/O (bank 1) |
| 핀 15 | I/O — General-purpose user I/O (bank 1) |
| 핀 16 | I/O — General-purpose user I/O (bank 1) |
| 핀 17 | I/O — General-purpose user I/O (bank 1) |
| 핀 18 | I/O — General-purpose user I/O (bank 1) |
| 핀 19 | I/O — General-purpose user I/O (bank 1) |
| 핀 20 | I/O — General-purpose user I/O (bank 1) |
| 핀 21 | I/O — General-purpose user I/O (bank 2) |
| 핀 22 | I/O — General-purpose user I/O (bank 2) |
| 핀 23 | I/O — General-purpose user I/O (bank 2) |
| 핀 24 | I/O — General-purpose user I/O (bank 2) |
| 핀 25 | I/O — General-purpose user I/O (bank 2) |
| 핀 26 | I/O — General-purpose user I/O (bank 2) |
| 핀 27 | I/O — General-purpose user I/O (bank 2) |
| 핀 28 | I/O — General-purpose user I/O (bank 2) |
| 핀 29 | I/O — General-purpose user I/O (bank 2) |
| 핀 30 | GND — Ground |
| 핀 31 | I/O — General-purpose user I/O (bank 2) |
| 핀 32 | I/O — General-purpose user I/O (bank 2) |
| 핀 33 | I/O — General-purpose user I/O (bank 2) |
| 핀 34 | I/O — General-purpose user I/O (bank 2) |
| 핀 35 | I/O — General-purpose user I/O (bank 2) |
| 핀 36 | I/O — General-purpose user I/O (bank 2) |
| 핀 37 | I/O — General-purpose user I/O (bank 2) |
| 핀 38 | I/O — General-purpose user I/O (bank 2) |
| 핀 39 | I/O — General-purpose user I/O (bank 2) |
| 핀 40 | I/O — General-purpose user I/O (bank 2) |
| 핀 41 | GND — Ground |
| 핀 42 | I/O — General-purpose user I/O (bank 3) |
| 핀 43 | I/O — General-purpose user I/O (bank 3) |
| 핀 44 | I/O — General-purpose user I/O (bank 3) |
| 핀 45 | I/O — General-purpose user I/O (bank 3) |
| 핀 46 | I/O — General-purpose user I/O (bank 3) |
| 핀 47 | I/O — General-purpose user I/O (bank 3) |
| 핀 48 | I/O — General-purpose user I/O (bank 3) |
| 핀 49 | I/O — General-purpose user I/O (bank 3) |
| 핀 50 | I/O — General-purpose user I/O (bank 3) |
| 핀 51 | I/O — General-purpose user I/O (bank 3) |
| 핀 52 | GND — Ground |
| 핀 53 | I/O — General-purpose user I/O (bank 3) |
| 핀 54 | I/O — General-purpose user I/O (bank 3) |
| 핀 55 | I/O — General-purpose user I/O (bank 3) |
| 핀 56 | I/O — General-purpose user I/O (bank 3) |
| 핀 57 | I/O — General-purpose user I/O (bank 3) |
| 핀 58 | I/O — General-purpose user I/O (bank 3) |
| 핀 59 | I/O — General-purpose user I/O (bank 3) |
| 핀 60 | I/O — General-purpose user I/O (bank 3) |
| 핀 61 | I/O — General-purpose user I/O (bank 4) |
| 핀 62 | I/O — General-purpose user I/O (bank 4) |
| 핀 63 | GND — Ground |
| 핀 64 | I/O — General-purpose user I/O (bank 4) |
| 핀 65 | I/O — General-purpose user I/O (bank 4) |
| 핀 66 | I/O — General-purpose user I/O (bank 4) |
| 핀 67 | I/O — General-purpose user I/O (bank 4) |
| 핀 68 | I/O — General-purpose user I/O (bank 4) |
| 핀 69 | I/O — General-purpose user I/O (bank 4) |
| 핀 70 | I/O — General-purpose user I/O (bank 4) |
| 핀 71 | I/O — General-purpose user I/O (bank 4) |
| 핀 72 | I/O — General-purpose user I/O (bank 4) |
| 핀 73 | I/O — General-purpose user I/O (bank 4) |
| 핀 74 | GND — Ground |
| 핀 75 | I/O — General-purpose user I/O (bank 4) |
| 핀 76 | I/O — General-purpose user I/O (bank 4) |
| 핀 77 | I/O — General-purpose user I/O (bank 4) |
| 핀 78 | I/O — General-purpose user I/O (bank 4) |
| 핀 79 | I/O — General-purpose user I/O (bank 4) |
| 핀 80 | I/O — General-purpose user I/O (bank 4) |
| 핀 81 | I/O — General-purpose user I/O (bank 4) |
| 핀 82 | I/O — General-purpose user I/O (bank 4) |
| 핀 83 | I/O — General-purpose user I/O (bank 4) |
| 핀 84 | I/O — General-purpose user I/O (bank 4) |
| 핀 85 | GND — Ground |
| 핀 86 | I/O — General-purpose user I/O (bank 5) |
| 핀 87 | I/O — General-purpose user I/O (bank 5) |
| 핀 88 | I/O — General-purpose user I/O (bank 5) |
| 핀 89 | I/O — General-purpose user I/O (bank 5) |
| 핀 90 | I/O — General-purpose user I/O (bank 5) |
| 핀 91 | I/O — General-purpose user I/O (bank 5) |
| 핀 92 | I/O — General-purpose user I/O (bank 5) |
| 핀 93 | I/O — General-purpose user I/O (bank 5) |
| 핀 94 | I/O — General-purpose user I/O (bank 5) |
| 핀 95 | I/O — General-purpose user I/O (bank 5) |
| 핀 96 | GND — Ground |
| 핀 97 | I/O — General-purpose user I/O (bank 5) |
| 핀 98 | I/O — General-purpose user I/O (bank 5) |
| 핀 99 | I/O — General-purpose user I/O (bank 5) |
| 핀 100 | I/O — General-purpose user I/O (bank 5) |
| 핀 101 | I/O — General-purpose user I/O (bank 5) |
| 핀 102 | I/O — General-purpose user I/O (bank 5) |
| 핀 103 | I/O — General-purpose user I/O (bank 5) |
| 핀 104 | I/O — General-purpose user I/O (bank 5) |
| 핀 105 | I/O — General-purpose user I/O (bank 5) |
| 핀 106 | I/O — General-purpose user I/O (bank 5) |
| 핀 107 | GND — Ground |
| 핀 108 | I/O — General-purpose user I/O (bank 6) |
| 핀 109 | I/O — General-purpose user I/O (bank 6) |
| 핀 110 | I/O — General-purpose user I/O (bank 6) |
| 핀 111 | I/O — General-purpose user I/O (bank 6) |
| 핀 112 | I/O — General-purpose user I/O (bank 6) |
| 핀 113 | I/O — General-purpose user I/O (bank 6) |
| 핀 114 | I/O — General-purpose user I/O (bank 6) |
| 핀 115 | I/O — General-purpose user I/O (bank 6) |
| 핀 116 | I/O — General-purpose user I/O (bank 6) |
| 핀 117 | I/O — General-purpose user I/O (bank 6) |
| 핀 118 | GND — Ground |
| 핀 119 | I/O — General-purpose user I/O (bank 6) |
| 핀 120 | I/O — General-purpose user I/O (bank 6) |
| 핀 121 | I/O — General-purpose user I/O (bank 6) |
| 핀 122 | I/O — General-purpose user I/O (bank 6) |
| 핀 123 | I/O — General-purpose user I/O (bank 6) |
| 핀 124 | I/O — General-purpose user I/O (bank 6) |
| 핀 125 | I/O — General-purpose user I/O (bank 6) |
| 핀 126 | I/O — General-purpose user I/O (bank 6) |
| 핀 127 | I/O — General-purpose user I/O (bank 6) |
| 핀 128 | I/O — General-purpose user I/O (bank 6) |
| 핀 129 | GND — Ground |
| 핀 130 | I/O — General-purpose user I/O (bank 1) |
| 핀 131 | I/O — General-purpose user I/O (bank 1) |
| 핀 132 | I/O — General-purpose user I/O (bank 1) |
| 핀 133 | I/O — General-purpose user I/O (bank 1) |
| 핀 134 | I/O — General-purpose user I/O (bank 1) |
| 핀 135 | I/O — General-purpose user I/O (bank 1) |
| 핀 136 | I/O — General-purpose user I/O (bank 1) |
| 핀 137 | I/O — General-purpose user I/O (bank 1) |
| 핀 138 | I/O — General-purpose user I/O (bank 1) |
| 핀 139 | I/O — General-purpose user I/O (bank 1) |
| 핀 140 | GND — Ground |
| 핀 141 | I/O — General-purpose user I/O (bank 1) |
| 핀 142 | I/O — General-purpose user I/O (bank 1) |
| 핀 143 | I/O — General-purpose user I/O (bank 1) |
| 핀 144 | I/O — General-purpose user I/O (bank 1) |
| 핀 145 | I/O — General-purpose user I/O (bank 1) |
| 핀 146 | I/O — General-purpose user I/O (bank 1) |
| 핀 147 | I/O — General-purpose user I/O (bank 1) |
| 핀 148 | I/O — General-purpose user I/O (bank 1) |
| 핀 149 | I/O — General-purpose user I/O (bank 1) |
| 핀 150 | I/O — General-purpose user I/O (bank 1) |
| 핀 151 | GND — Ground |
| 핀 152 | TDI — JTAG Test Data In |
| 핀 153 | TMS — JTAG Test Mode Select |
| 핀 154 | TCK — JTAG Test Clock |
| 핀 155 | TDO — JTAG Test Data Out |
| 핀 156 | GND — Ground |
| 핀 157 | VCC — 5.0 V supply (4.75 V to 5.25 V) |
| 핀 158 | VCC — 5.0 V supply (4.75 V to 5.25 V) |
| 핀 159 | GLOBALCLK1 — Global clock input 1 |
| 핀 160 | GLOBALCLK2 — Global clock input 2 / OE |
일반적인 애플리케이션
EPM7160SQC160-7 적합 용도: 6 애플리케이션s: PCI Bus Glue Logic, Microprocessor to Memory Address Decoding, Bus-Width Translation (5 V to 3.3 V), State-Machine Replacement for Discrete PALs, Peripheral Controller Glue Logic, Industrial Control and Instrumentation Logic.
PCI Bus Glue Logic
The EPM7160SQC160-7's PCI-SIG 2.2 compliance and 104 user I/Os make it a natural fit for PCI target/host adapter glue logic. The 7.5 ns tPD allows state-machine decoding of PCI address/command phases within the 33 MHz bus clock period. Place the device between the PCI bus transceivers and the local controller to handle parity generation, target response, and burst-handling state. Compared to discrete 22V10 PALs, the 160-macrocell capacity consolidates what would otherwise require 4-6 SPLDs onto one BQFP-160 footprint.
추천
Microprocessor to Memory Address Decoding
In 8/16/32-bit embedded systems the EPM7160SQC160-7 replaces multiple 22V10 / GAL22V10 devices with a single 160-macrocell CPLD, generating chip-select signals for ROM, SRAM, DRAM, and peripheral banks. The 5.0 V VCC with selectable 3.3 V or 5.0 V output levels allows direct interfacing to both legacy 5 V memory and modern 3.3 V peripherals without external level shifters. The 7.5 ns tPD keeps the decoded chip-select valid before the memory access window opens at typical 25-40 MHz CPU clock rates.
추천
Bus-Width Translation (5 V to 3.3 V)
The EPM7160SQC160-7's selectable 3.3 V or 5.0 V output drivers per I/O bank enable mixed-voltage bus translation without external level-shift ICs. A 160-macrocell device comfortably implements a 32-bit bidirectional 5 V <-> 3.3 V translator with direction-control logic. The 7.5 ns tPD supports bus throughput up to ~66 MHz, suitable for legacy peripheral buses in industrial PCs and instrumentation where 5 V cores still coexist with 3.3 V ASICs.
추천
State-Machine Replacement for Discrete PALs
Engineers use the EPM7160SQC160-7 to consolidate boards originally built with 4-8 discrete PAL/GAL devices into a single CPLD, freeing PCB area and reducing BOM cost. The EEPROM-backed configuration is non-volatile, providing instant-on behavior at power-up - critical for industrial controllers where a slow FPGA boot is unacceptable. With 32 product terms per macrocell and 10 LABs, the device can host multiple independent state machines plus combinational decode in one chip, all running at the guaranteed 7.5 ns tPD.
추천
Peripheral Controller Glue Logic
The EPM7160SQC160-7 serves as the central glue-logic hub on legacy peripheral controller boards, interfacing microprocessors to UARTs, FIFOs, DMA controllers, and interrupt controllers. The 104 user I/Os and 3,200-gate capacity provide ample headroom for FIFO flag combining, interrupt prioritization, and timing generation. JTAG-based in-system programmability allows field firmware updates without removing the controller card from its host chassis - a key advantage over one-time-programmable PALs.
추천
Industrial Control and Instrumentation Logic
In industrial automation backplanes and test-and-measurement instruments, the EPM7160SQC160-7 delivers deterministic, non-volatile logic for custom timing, signal routing, and protection interlocks. The commercial 0-70 °C operating range covers most indoor enclosures, and the 5 V tolerance interfaces directly to legacy industrial sensors and actuators. The device's instant-on EEPROM configuration eliminates boot-loader complexity, making it ideal for safety-critical interlocks that must be active before the main CPU boots.
추천
추천 제품 요약
엔지니어링 참조 데이터: EPM7160SQC160-7 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EPM7160SQC160-6 | EPM7160SQC160-10 | EPM7160SQC160-10N | EPM7160EQC160-12 |
|---|---|---|---|---|---|
| Package | 160-pin PQFP (BQFP, 28x28 mm) | 160-pin PQFP (BQFP) - same | 160-pin PQFP (BQFP) - same | 160-pin PQFP (BQFP) - same | 160-pin PQFP (BQFP) - same |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Speed Grade | -7 (7.5 ns tPD) | -6 (6 ns tPD) | -10 (10 ns tPD) | -10 (10 ns tPD) | -12 (12 ns tPD, MAX 7000E) |
| Macrocells | 160 | 160 | 160 | 160 | 160 |
| System Gates | 3,200 | 3,200 | 3,200 | 3,200 | 3,200 |
| Family | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000E |
| RoHS Status | Not Compliant | Not Compliant | Not Compliant | Lead-free / RoHS | Not Compliant |
| Operating Temperature | 0 to 70 °C (commercial) | 0 to 70 °C | 0 to 70 °C | 0 to 70 °C | 0 to 70 °C |
주요 차별점
- Balanced speed-cost point in the MAX 7000S speed-grade family (vs EPM7160SQC160-6)
- PCI-SIG 2.2 compliant glue logic in a single chip (vs Discrete 22V10 / GAL22V10 PAL array)
- 5 V tolerant with selectable 3.3 V I/O for mixed-voltage designs (vs MAX V CPLD (5M160ZE64) active-lifecycle alternative)
설계 노트
The EPM7160SQC160-7 requires a single 5.0 V supply (4.75 V to 5.25 V). Decouple each VCC/GND pair with a 0.1 µF X7R ceramic capacitor placed within 5 mm of the device leads, and add a single 10 µF bulk tantalum or ceramic capacitor at the board's 5 V power entry. During in-system programming (ISP), transient current can briefly exceed the steady-state ICC; ensure the regulator has at least 200 mA headroom. Power sequencing is not required - the device enters user mode automatically after POR.
Route the four JTAG signals (TDI, TMS, TCK, TDO) as a short daisy-chain with 10 kΩ pull-ups on TMS and TDI; keep total JTAG trace length below 50 mm to maintain signal integrity at typical 10-20 MHz TCK rates. The 160-pin PQFP (28x28 mm body) requires a 4-layer PCB with a solid ground plane beneath the device to provide a low-impedance return path for the 104 high-speed I/Os. Leave the four corner GND pins (11, 30, 41, 52, 63, 74, 85, 96, 107, 118, 129, 140, 151, 156) solidly stitched to the ground plane with multiple vias each for thermal and electrical performance.
Three pitfalls are common when migrating designs to or from the EPM7160SQC160-7. First, do not assume the I/O banks default to 5 V - the output level is set by VCCIO per bank and must be explicitly connected even when only one voltage is used. Second, do not exceed 104 user I/Os in your pin assignment; the datasheet's 'Maximum' count assumes all dedicated JTAG and global clock pins are re-purposed as I/O, which is rarely desirable. Third, when replacing with the EPM7160SQC160-6 or -10 speed grade, verify timing closure - the 25% speed delta (-10 vs -7) can break PCI-bus designs.
규정 준수 정보
Per Arrow listing: EU RoHS Not Compliant; ECCN EAR99; SVHC declaration Yes. Use EPM7160SQC160-10N suffix variant for lead-free / RoHS-compliant assembly. AEC-Q100 not applicable (commercial-grade part).
