DS90CF364MTD
DS90CF364MTD - 65 MHz 18-Bit LVDS Receiver | Texas Instruments
The Texas Instruments DS90CF364MTD is a 3.3 V LVDS receiver for an 18-bit flat-panel display link, operating at up to 65 MHz and supporting three LVDS data streams in a 48-TSSOP package. It converts differential LVDS data back into CMOS/TTL signals for display timing, control, and pixel-data recovery. The receiver is designed for high-speed panel interfaces where reducing cable size, connector count, and EMI susceptibility is important.
An LVDS receiver is an interface-circuit component that restores low-voltage differential signaling into digital logic levels. In the broader hierarchy, it belongs to the LVDS interface family, then to serializers, deserializers, and interface ICs used in display and communications systems. LVDS transmits complementary signals over a balanced pair, allowing reliable data transfer across cables or PCB interconnects while limiting common-mode noise and radiated emissions.
The DS90CF364MTD supports an 18-bit RGB data path with LCD timing and control signals, including FPLINE, FPFRAME, and DRDY. At a 65 MHz transmit-clock frequency, the link carries 455 Mbps per LVDS data channel according to the manufacturer product information. The receiver is intended to pair with the DS90C363 transmitter family, whose programmable rising- or falling-edge strobe operation allows interoperability with the falling-edge receiver.
The device operates from a 3.3 V supply and is packaged in a surface-mount 48-TSSOP package. Its receiver architecture is designed for point-to-point display links, where the transmitter, receiver, cable, and connector form a controlled differential channel. The package and interface arrangement support compact display-controller boards while keeping the high-speed differential traces physically separate from sensitive analog and control circuitry.
Typical applications include LCD and flat-panel monitor interfaces, digital signage, industrial HMIs, automotive display links, test equipment, and embedded video systems. In each case, the DS90CF364MTD can reduce parallel bus width and connector pin count while preserving an 18-bit display data path. System designers should still validate signal integrity, connector geometry, cable length, and grounding against the specific display and transmitter implementation.
A primary design consideration is that LVDS performance depends on the complete channel, not only the receiver IC. Use controlled-impedance PCB routing, a suitable differential pair geometry, compliant input-capacitance loading, and the power and ground connections specified by the manufacturer datasheet. Keep the receiver away from noisy switching nodes and place bypassing close to the device supply pins.
This product page combines the manufacturer interface description, package information, application guidance, and practical considerations for engineers evaluating the DS90CF364MTD in a flat-panel display link. The information helps distinguish receiver function, channel rate, voltage, package, and system-level design responsibilities before a prototype PCB is released.
견적 요청
문의하기
