DS90C387VJD - 48-Bit Dual-Pixel LVDS Transmitter | TI
부품 번호: DS90C387VJD ✗ 단종DS90C387VJD 개요
A dual-pixel LVDS display interface is a high-speed display-link interface in which two pixels are transmitted in parallel over multiple low-voltage differential signaling lanes. LVDS belongs to the differential-interface hierarchy used to move high-speed pixel data reliably between a display controller or graphics source and a flat-panel display. Reducing the number of transmitted signal lines helps shorten PCB routing while preserving high aggregate data throughput.
The DS90C387VJD accepts 48 bits representing dual 24-bit pixel data and converts them into eight differential LVDS streams. During blanking periods, it also sends control information including VSYNC, HSYNC, DE, and two user-defined signals. These functions allow synchronization and control traffic to share the physical link instead of requiring a separate interface for every control function.
The verified manufacturer information identifies the part as a dual-pixel transmitter for SVGA and QXGA display systems. It operates from a +3.3 V supply and is packaged in a surface-mount 100-pin TQFP configuration. The part-details listing carries the NEZ lifecycle designation, while the supplied data gives an operating-temperature range of -10 °C to +70 °C. Detailed electrical limits, LVDS output voltage, propagation delay, pixel-clock range, and pin-level signal definitions were not included in the supplied records and therefore are not inferred here.
Typical display applications include desktop flat-panel monitors, industrial panel interfaces, and embedded display systems that use the DS90C387/DS90CF388 transmitter-receiver pairing. In these systems, the DS90C387VJD handles parallel CMOS/TTL pixel input and low-voltage differential output, while a compatible receiver at the panel converts the differential data back into logic-level signals.
The primary design consideration is PCB signal integrity. Eight LVDS data outputs require controlled impedance routing, minimized stubs, appropriate layer transitions, and placement of receiver termination close to the receiving device. The 100-pin package also requires adequate via-in-pad or through-hole fanout under fine-pitch leads, along with deliberate grounding and supply-decoupling layout.
This page combines the verified Texas Instruments product description, package and lifecycle information, distributor identification, and cross-reference results. It also distinguishes documented order variants from genuinely supported drop-in alternatives and highlights the electrical and lifecycle values that still require confirmation from the complete manufacturer datasheet.
드롭인 대체품: DS90C387VJD — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
DS90C387AVJD
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DS90C387VJDX
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DS90C387VHG
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DS90C387VJD 사양
| Product Type | Dual-pixel LVDS display interface transmitter |
| 공급 전압 | +3.3 V |
| Input Data Width | 48 bits |
| LVDS Data Streams | 8 |
| Supported Resolution | Up to QXGA |
| Pixel Organization | Dual pixel, 24-bit color per pixel |
| Input Signal Type | CMOS/TTL |
| Output Signal Type | LVDS differential signaling |
| Blanking-Period Control Signals | VSYNC, HSYNC, DE, and 2 user-defined signals |
| Driver Channel Count | 8 channels |
| Receiver Channel Count | 0 channels |
| 패키지 | 100-pin TQFP (NEZ), 14 x 14 mm |
| 핀 수 | 100 pins |
| 실장 유형 | Surface mount |
| 동작 온도 범위 | -10 °C to +70 °C |
| Lifecycle Designation | NEZ |
DS90C387VJD 100-pin tqfp (nez), 14 x 14 mm 핀 구성 가이드
DS90C387VJD(100-pin tqfp (nez), 14 x 14 mm 패키지)의 핀 구성입니다. 핀 번호, 기능, 연결 다이어그램은 제조사 데이터시트에 정의되어 있습니다. 정확한 풋프린트와 솔더링 지침은 해당 문서를 참조하십시오.
다음에 대한 상세 핀아웃 데이터 없음: DS90C387VJD.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
DS90C387VJD 적합 용도: 6 애플리케이션s: Desktop Flat-Panel Monitor Interface, Industrial Panel Controller Interface, Embedded Human-Machine Interface Display, Instrumentation Video Panel, Digital Signage Controller, Dual-Pixel Display Test System.
Desktop Flat-Panel Monitor Interface
The DS90C387VJD fits a desktop monitor link in which a graphics controller supplies 48 bits of dual-pixel CMOS/TTL data and the panel requires eight LVDS lanes. It converts the parallel pixel information into eight differential streams while carrying VSYNC, HSYNC, DE, and two user-defined signals during blanking. The documented QXGA capability provides a clear use-case match for dual-pixel LCD panel controllers. Compared with routing many parallel pixel lines, the LVDS architecture reduces signal count, but it requires carefully controlled differential impedance and short, matched routing to preserve timing and minimize electromagnetic interference.
추천
Industrial Panel Controller Interface
The DS90C387VJD is appropriate for an industrial panel connection that receives dual-pixel, 24-bit-color data from a controller and carries it to a remote display over LVDS. Its 48-bit parallel input and eight LVDS outputs provide a documented mapping for SVGA and QXGA systems, while blanking-period control signals support display synchronization without additional wiring. The listed -10 °C to +70 °C range is suitable for many indoor industrial environments, but designers must verify enclosure temperature and EMC requirements. PCB routing should use matched LVDS geometry, avoid stubs, and provide a continuous return path beneath the differential pairs.
추천
Embedded Human-Machine Interface Display
An embedded HMI can place the DS90C387VJD between a compact display engine and a larger LVDS panel when the engine provides 48-bit dual-pixel parallel data. The transmitter organizes the data into eight differential outputs, reducing the number of high-speed traces crossing the internal PCB and helping preserve signal integrity. Synchronization and data-enable information is transferred during blanking, allowing the panel to remain coordinated with the source. The implementation trade-off is that the transmitter is not a general-purpose graphics processor: timing, panel configuration, and LVDS receiver termination must be designed around the DS90C387 family requirements.
추천
Instrumentation Video Panel
Test and measurement instruments can use the DS90C387VJD to connect a graphics or frame-buffer source to an LVDS display panel. The documented 48-bit dual-pixel input supports high-color panel data, and eight LVDS outputs provide a practical high-speed transport for QXGA-class displays. Control signals are sent during blanking, helping the display maintain frame and line synchronization. Because the verified record does not specify EMI classifications or timing margins, instrument designers should perform their own conducted and radiated emissions checks. Short differential routes, controlled reference planes, and careful grounding are essential around the 100-pin TQFP transmitter.
추천
Digital Signage Controller
A digital-signage controller can use the DS90C387VJD when it drives a dual-pixel panel from a source capable of supplying 48-bit CMOS/TTL pixel data. The transmitter converts that information into eight LVDS streams and transfers synchronization information during blanking, supporting a cleaner panel connection than a wide parallel-pixel bus. Its QXGA capability makes it relevant to larger embedded signs, provided the source timing matches the display controller requirements. The main engineering challenge is maintaining consistent rise and fall times across eight differential pairs while avoiding vias, stubs, and unnecessary copper discontinuities that could degrade signal integrity.
추천
Dual-Pixel Display Test System
The DS90C387VJD can serve as the transmit-side device in a bench fixture that validates a dual-pixel LVDS panel or cable assembly. A test controller supplies 48 bits of CMOS/TTL pixel data, and the transmitter generates the eight differential outputs expected by the panel interface. VSYNC, HSYNC, DE, and two user-defined blanking signals provide additional points for synchronization testing. This use is particularly useful when characterizing signal integrity across connectors, cables, and adapters. Engineers should use controlled patterns and verify eye quality and timing at the receiver rather than inferring link margin solely from the transmitter's stated QXGA support.
추천
추천 제품 요약
엔지니어링 참조 데이터: DS90C387VJD — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | DS90C387AVJD | DS90C387VJDX | DS90C387VHG |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 100-TQFP (14 x 14 mm) | 100-TQFP (14 x 14 mm) | 100-TQFP (14 x 14 mm) | 100-TQFP (14 x 14 mm) |
| Product Type | Dual-pixel LVDS display interface transmitter | Dual-pixel LVDS display interface transmitter | Dual-pixel LVDS display interface transmitter | Dual-pixel LVDS display interface transmitter |
| Supply Voltage | +3.3 V | +3.3 V | +3.3 V | +3.3 V |
| Input Data Width | 48 bits | 48 bits | 48 bits | 48 bits |
| LVDS Output Streams | 8 | 8 | 8 | 8 |
| Supported Resolution | Up to QXGA | Up to QXGA | Up to QXGA | Up to QXGA |
| Driver Channel Count | 8 channels | 8 channels | 8 channels | 8 channels |
주요 차별점
- Documented eight-lane dual-pixel conversion (vs DS90C387AVJD)
- Direct QXGA-capable display-link function (vs DS90C387VJDX)
- Integrated blanking-period control transmission (vs DS90C387VHG)
설계 노트
Route all eight LVDS pairs as length-matched, tightly coupled differential traces on a continuous reference plane. Avoid stubs, test pads without proper series termination, and abrupt layer changes. Keep the receiver termination at the receiving device because incorrect resistor placement can materially alter edge rate and degrade signal integrity. The verified records do not specify the required LVDS characteristic impedance, so the value must be taken from the manufacturer datasheet and the actual PCB stack-up.
Place decoupling capacitors adjacent to the +3.3 V and ground pins, and provide a low-impedance via connection to the ground plane beneath the 100-pin TQFP. The package's 14 x 14 mm body and fine-pitch leads require careful escape routing: prioritize short power connections, minimize loop area, and use symmetrical fan-out patterns for the CMOS/TTL inputs. Do not route high-speed LVDS outputs beneath a noisy switching-regulator area or across a plane split.
Do not treat SN75LVDS83B as a board-level drop-in substitute merely because a search result groups it with equivalent products. The verified evidence does not establish a 100-pin pin-compatible dual-pixel display interface for that device. Likewise, confirm the meaning of each DS90C387 ordering suffix, especially temperature grade and lifecycle status, before replacing the target. Validate the complete 100-pin mapping, power rails, control-signal polarity, and receiver expectations against the official datasheet.
규정 준수 정보
The supplied verified records identify the manufacturer and NEZ lifecycle designation but do not provide explicit RoHS, REACH, AEC-Q100, lead-free, halogen-free, or conflict-minerals statements. No compliance claim has been inferred.
