5M80ZT100A5N vs 5M570ZT100A5N 비교
다음의 상세 나란히 비교: 5M80ZT100A5N 제조: Altera 및 5M570ZT100A5N 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | 5M80ZT100A5N | 5M570ZT100A5N |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 활성 | 활성 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $1.85 | $9.75 |
| Family | MAX V | MAX V |
| Macro Cells | 64 | — |
| Logic Elements / LABs | 8 Logic Array Blocks (LABs) | — |
| Maximum User I/O | 80 (in TQFP-100 package) | — |
| Pin-to-Pin Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Internal Frequency (fMAX) | 118.3 MHz | — |
| Core Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Bank Supply Voltage (VCCIO) | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-voltage banks) | — |
| User Flash Memory (UFM) | 8 Kbits (typical for MAX V 64-macrocell device) | — |
| Configuration Memory | Non-volatile, on-chip flash | On-chip non-volatile flash |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) | JTAG (IEEE 1149.1), in-system programmable (ISP) |
| 동작 접합 온도 | -40 C to +125 C (automotive/industrial grade) | — |
| 패키지 | 100-pin TQFP (T100) | 100-pin TQFP |
| 실장 유형 | Surface Mount | Surface Mount |
| MSL 레벨 | 3 (per JEDEC J-STD-020) | — |
| RoHS 상태 | Compliant | Compliant |
| Automotive Qualification | AEC-Q100 (A5N suffix) | AEC-Q100 (per Arrow listing) |
| Supply Current (typical) | [DATA_NEEDED: Icc typical] | — |
| Global Clock Networks | 4 | — |
| Lead-Free / Halogen-Free | Yes / Yes (per Altera lead-free roadmap) | — |
| Device Logic Elements | — | 570 |
| Macrocells | — | 440 |
| Logic Array Blocks (LABs) | — | 8 |
| Maximum User I/O Pins | — | 74 |
| Maximum Operating Frequency | — | 118.3 MHz |
| Pin-to-Pin Logic Delay (tPD) | — | 9.0 ns |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage (VCCIO) | — | 1.8 V / 2.5 V / 3.3 V (multi-voltage I/O banks) |
| Operating Temperature (A suffix) | — | -40C to +125C |
| Internal Oscillator | — | Yes (on-chip) |
| User Flash Memory | — | Yes (on-chip) |