EP1810LI-25 vs EP1810LC-35 비교
다음의 상세 나란히 비교: EP1810LI-25 제조: Altera 및 EP1810LC-35 제조: Rochester Electronics. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ 최종 구매사양 비교
| 파라미터 | EP1810LI-25 | EP1810LC-35 |
|---|---|---|
| 브랜드 | Altera | Rochester Electronics |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | 최종 구매 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.95 | $49.20 |
| Family | Altera Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device), UV-erasable / OTP | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 48 | 48 |
| Usable Gates | 900 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Counter Frequency | 40 MHz | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | 5 V (4.75 V to 5.25 V) |
| I/O Pins | 48 | [DATA_NEEDED: I/O count exact] |
| Dedicated Inputs | 12 | — |
| Global Clock Inputs | 4 | — |
| Interconnect | Programmable global and local buses | — |
| 패키지 | 68-pin PLCC (J68, J-Lead) | 68-pin PLCC (J-Lead) |
| JESD-30 Package Code | S-PQCC-J68 | — |
| Process Technology | CMOS | — |
| Operating Temperature (Industrial 'I' suffix) | -40 C to +85 C | — |
| Programming Mode | EPROM/UV-erasable (windowed) and OTP | — |
| Development Tool | Altera MAX+PLUS II | — |
| RoHS 상태 | unknown | [DATA_NEEDED] |
| Lead-Free Status | unknown | — |
| Series | — | Classic EP1810 |
| Equivalent Gates | — | 900 usable / 2100 equivalent |
| Maximum Operating Frequency | — | 28.6 MHz |
| Propagation Delay (tpd) | — | 35 ns (max, '-35' speed grade) |
| Technology | — | CMOS, UV-erasable EPROM |
| 실장 유형 | — | Surface Mount (socketable) |
| 동작 온도 | — | 0C to +70C (commercial) |
| Configuration Method | — | UV-erase + EPROM programmer |
| Programmable Interconnect | — | Centralized Programmable Interconnect Array (PIA) |
| Development Tool (legacy) | — | MAX+PLUS II / A+PLUS |
| Lead-Free | — | [DATA_NEEDED] |