EP1810LI-35 vs EP1810LC-25 비교
다음의 상세 나란히 비교: EP1810LI-35 제조: Altera 및 EP1810LC-25 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1810LI-35 | EP1810LC-25 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $78.05 | $8.40 |
| Manufacturer | Rochester Electronics, LLC (original Altera design) | — |
| Part Family | Altera Classic EPLD | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 35 ns | 25 ns |
| Speed Grade | 35 (slowest in EP1810L family) | — |
| 패키지 | 68-pin PLCC (J-Lead, plastic) | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Pin/Package Code | PLCC-68 / PQCC68 | — |
| Technology | CMOS, UV-erasable EPROM configuration cell | CMOS EPLD (erasable programmable logic device) |
| 공급 전압 | 5 V (TTL-compatible I/O) | — |
| 동작 온도 | -40 C to +85 C (industrial, 'I' suffix) | [DATA_NEEDED: temperature grade for LC package] |
| 실장 유형 | Surface Mount (PLCC socket compatible) | Surface Mount |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| Logic Elements | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL 레벨 | [DATA_NEEDED: MSL rating] | — |
| Product Family | — | Altera Classic EPLD |
| Part Number | — | EP1810LC-25 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 5 V (TTL-compatible) |
| Operating Mode | — | Turbo-only (no slow-power mode) |
| Package Code | — | LC = 68-pin JLCC |
| Programmable Interconnect | — | Global + Local buses |
| Programming Method | — | Altera Classic programmer + MAX+PLUS II legacy flow |
| 수명 주기 상태 | — | Obsolete (legacy Altera Classic family) |