EP1K50QC208-3N vs EP1K50QC208-1N 비교
다음의 상세 나란히 비교: EP1K50QC208-3N 제조: Altera 및 EP1K50QC208-1N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1K50QC208-3N | EP1K50QC208-1N |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | 활성 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $13.85 | $0.00 |
| Family | ACEX-1K | ACEX 1K |
| Typical Gates | 50,000 | — |
| Logic Elements (LEs) | 2,880 | — |
| Logic Array Blocks (LABs) | 360 | — |
| Embedded RAM | 40,960 bits (10 EABs × 4,096 bits) | — |
| Maximum User I/Os | 147 | — |
| Maximum Operating Frequency | 166.67 MHz | 250 MHz |
| Pin-to-Pin Logic Delay | 0.5 ns (typical, -3 speed grade) | — |
| Process Technology | 0.22 µm CMOS | 0.22 um CMOS |
| Core Supply Voltage (VCCINT) | 2.5 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V (PCI-compatible I/O banks) | — |
| 패키지 | 208-pin PQFP / BFQFP (Plastic Quad Flat Pack) | — |
| 실장 유형 | Surface Mount | Surface Mount |
| 동작 온도 | 0 °C to +70 °C (Commercial) | — |
| Programming Interface | IEEE 1149.1 JTAG + in-system configurable | — |
| Lead-Free / RoHS | Compliant (Pb-free terminal finish per 'N' suffix) | — |
| Product Type | — | Field Programmable Gate Array (FPGA) |
| Number of Logic Elements | — | 2880 LE |
| Number of LABs | — | 360 LABs |
| Embedded Memory Bits | — | 40960 bits (40 kbit) |
| Embedded RAM Capability | — | RAM, ROM, dual-port RAM, FIFO (per ACEX 1K architecture) |
| Maximum User I/O | — | 147 I/O |
| Typical Gate Count | — | 50000 gates |
| Core Supply Voltage | — | 2.5 V |
| Speed Grade | — | -1 |
| Package Type | — | 208-BFQFP (PQFP-208) |
| Terminal Form | — | Gull wing |
| Package Shape | — | Square |
| Lead-Free Finish | — | N suffix, lead-free finish per Altera part numbering |
| 동작 온도 범위 | — | [DATA_NEEDED: exact operating temperature range] |