EP1M350F780I5 vs EP1M350F780C6N 비교
다음의 상세 나란히 비교: EP1M350F780I5 제조: Altera 및 EP1M350F780C6N 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EP1M350F780I5 - Altera Mercury Enhanced Configuration Device, 780-pin FBGA | Intel
EP1M350F780I5 Nrnd사양 비교
| 파라미터 | EP1M350F780I5 | EP1M350F780C6N |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | 최종 구매 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $178.00 | $219.40 |
| Device Family | Altera Mercury (EP1M) Enhanced Configuration Device | — |
| 기능 | FPGA configuration PROM with integrated controller | — |
| Storage Density Code | 350 (high-density) | — |
| Supported Configuration Schemes | Passive Serial, Active Serial, Fast Passive Parallel | — |
| Internal Architecture | Configuration controller + flash memory array | — |
| Programming Method | In-system programmable via Altera Quartus / JTAG | — |
| 패키지 | 780-ball FineLine BGA (F780) | 780-ball FC-FBGA (FINE LINE BGA-780) |
| Temperature Grade (suffix "I") | Industrial | — |
| Speed Grade | 5 | — |
| Target FPGA Compatibility | Altera APEX 20K, APEX II, Mercury, Stratix-class high-density FPGAs | — |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) | — |
| Cascade / Multi-FPGA Support | Yes, supports daisy-chained multi-FPGA boot | — |
| Read-Back | Yes | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs_status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead_free] |
| Family | — | Mercury (EP1M350) |
| Device Type | — | Loadable Programmable Logic Device (PLD) / FPGA |
| Logic Family | — | CMOS, SRAM-based LUT |
| System Gates | — | 350,000 |
| Logic Cells / Elements | — | 14,400 |
| User I/Os | — | 486 |
| Integrated Transceivers | — | Yes, with CDR up to 1.25 Gbps |
| Core Supply Voltage | — | 1.8 V |
| Terminal Form | — | Ball |
| Package Code (JEDEC) | — | S-PBGA-B780 |
| 동작 온도 | — | 0 C to 85 C |
| Configuration Interface | — | JTAG (IEEE 1149.1) / passive serial |
| MSL 레벨 | — | [DATA_NEEDED: msl_level] |
| Architecture | — | Look-up table (LUT)-based, optimized for high-speed serial I/O |
| Total Package Pins / Balls | — | 780 |