EP1SGX25CF672C7 vs EP1SGX25DF67216 비교

다음의 상세 나란히 비교: EP1SGX25CF672C7 제조: Altera 및 EP1SGX25DF67216 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EP1SGX25CF672C7 EP1SGX25DF67216
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $340.00 $198.00
Family Stratix® GX Stratix GX
Logic Elements / Cells 25,660 —
Logic Array Blocks (LABs) 2,566 —
Total RAM Bits 1,944,576 1,944,576
Maximum User I/O 455 —
Number of I/Os 455 —
Core Supply Voltage 1.5 V 1.5 V
Process Technology 130 nm CMOS —
동작 온도 0 °C to 85 °C (commercial, C-grade) Industrial, -40C to +100C (I-suffix family)
실장 유형 Surface Mount Surface Mount (BGA)
패키지 672-ball FC-FBGA, 33 × 33 mm, 1.0 mm pitch 672-ball FineLine BGA (DF672)
RoHS 상태 RoHS non-compliant (variant as listed); Pb-free / RoHS versions use "N" suffix Lead-free / RoHS compliant (per Altera product family documentation)
Configuration Method Passive Serial / Fast Passive Parallel / JTAG —
Device Series Stratix GX (SGX) —
Lead-Free / Pb-Free Lead-free package, RoHS status varies by suffix —
Logic Elements — 25,660
Embedded Multipliers (18x18) — [DATA_NEEDED: 18x18 multiplier count]
Number of PLLs — 4
Number of Transceiver Channels — 8 (4 in each of 2 banks)
Max Transceiver Data Rate — 3.1875 Gbps per channel
Min Transceiver Data Rate — 500 Mbps
Auxiliary Supply Voltage — 3.3 V
I/O Supply Voltage — 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank)
Maximum User I/O Pins — [DATA_NEEDED: user I/O count for DF672 package]
On-Die Termination — Yes, 100-ohm differential
Pre-emphasis / Equalization — Programmable (transmitter pre-emphasis; receiver adaptive equalization)
Configuration Schemes — Passive serial, fast passive parallel, JTAG, Altera enhanced configuration

데이터시트 & 자료

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