EP20K200CF484I9 vs EP20K200CF484I7 비교
다음의 상세 나란히 비교: EP20K200CF484I9 제조: Altera 및 EP20K200CF484I7 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP20K200CF484I9 | EP20K200CF484I7 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | 최종 구매 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $138.00 | $89.50 |
| Series | APEX 20KC | — |
| Family | APEX 20KC (APEX 20K with ESB/CAM) | APEX 20KC |
| Process Technology | 0.15 um CMOS | 0.15 µm CMOS with copper interconnect |
| Typical Gates | 200,000 | — |
| Logic Elements (Cells) | 8,320 | — |
| Maximum User I/O | 376 | — |
| Dedicated Inputs | 4 | 4 |
| Total Terminals | 484 (balls) | — |
| 패키지 | 484-ball FineLine BGA (FBGA), 1.00 mm pitch | 484-pin FBGA (FineLine BGA) |
| Core Supply Voltage (VCCINT) | 1.8 V nominal (1.71 V to 1.89 V) | — |
| Operating Temperature Grade | Industrial (I) | — |
| Junction Temperature Range | -40 C to +100 C | — |
| Speed Grade | -9 (lowest speed in EP20K200 family) | -7 |
| Configuration Method | SRAM, JTAG in-system programmable | — |
| RoHS 상태 | unknown - confirm with supplier (legacy part) | [DATA_NEEDED: RoHS compliance status] |
| Lifecycle | Obsolete - EOL announced by Altera/Intel in 2008 | — |
| Logic Elements | — | 8,320 |
| Typical Gate Count | — | 200,000 system gates |
| Maximum Operating Frequency | — | 375.94 MHz (per device-family data) |
| Internal Supply Voltage (VCCINT) | — | 1.8 V (1.71 V to 1.89 V) |
| I/O Supply Voltage (VCCIO) | — | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) |
| User I/O Pins | — | 376 |
| Package Body Size | — | 23 mm × 23 mm |
| Ball Pitch | — | 1.000 mm |
| Temperature Grade (I7 suffix) | — | Industrial, -40 °C to +85 °C |
| Configuration Technology | — | SRAM-based, re-programmable in-system |
| Propagation Delay | — | [DATA_NEEDED: datasheet-specified tpd] |