EP20K400GC655-3V vs EP20K400GC655-3X 비교
다음의 상세 나란히 비교: EP20K400GC655-3V 제조: Intel 및 EP20K400GC655-3X 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP20K400GC655-3V | EP20K400GC655-3X |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $160.00 | $65.00 |
| Series | APEX-20KC | APEX-20KC |
| Family | APEX 20KC (Apex 20KE Device Family, 1.8 V, LVDS) | APEX 20K (MultiCore architecture, LUT + product-term + embedded memory) |
| Manufacturer | Altera (now Intel) | Altera (now Intel FPGA) |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V nominal) | — |
| Logic Elements | 16640 | — |
| Total RAM Bits | 212992 | 212,992 bits |
| Typical Gate Count | 400000 | — |
| Number of User I/O | 496 | — |
| 최대 클록 주파수 | 714.2 MHz | — |
| Propagation Delay | 3.6 ns | — |
| Speed Grade | -3V (commercial temperature, Vcc 1.8 V) | -3 (fastest) |
| 패키지 | 655-BCPGA (62.48 mm x 62.48 mm) | — |
| Package Equivalence Code | SPGA655, 47x47 | — |
| 실장 유형 | Through Hole (CPGA) | Through-Hole (CPGA, ceramic) |
| Peak Reflow Temperature | 220 C | — |
| Process Technology | CMOS | 0.22 µm CMOS |
| Configuration | SRAM-based (requires EPC configuration device) | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance flag - BCPGA package often non-RoHS] | [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS] |
| 동작 온도 | [DATA_NEEDED: commercial / industrial / military grade] | [DATA_NEEDED: operating temperature range] |
| Logic Elements / Cells | — | 16,640 |
| System Gates | — | 400,000 |
| Maximum Internal Frequency | — | 167 MHz (speed grade -3) |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V (LVDS support per APEX 20KE datasheet) |
| 패키지 / 케이스 | — | 655-BCPGA (CPGA655, 62.48 x 62.48 mm) |
| Suffix Code | — | -X (extended / ceramic CPGA variant) |
| I/O Count | — | [DATA_NEEDED: max user I/O] |
| JTAG / Boundary Scan | — | IEEE 1149.1 (per APEX 20K family) |