EP2A40B724I8N vs EP2A40B724CP 비교
다음의 상세 나란히 비교: EP2A40B724I8N 제조: Altera 및 EP2A40B724CP 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP2A40B724I8N | EP2A40B724CP |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $138.75 | $71.00 |
| Series | APEX II (EP2A40) | — |
| Device Family | APEX II Field Programmable Gate Array | — |
| Manufacturer | Altera (now Intel PSG) | — |
| Logic Cells / Elements | 38,400 | — |
| System Gates | 1,500,000 (1.5 M) | — |
| Maximum User I/O | 536 | — |
| Terminal Count (Package Pins/Balls) | 724 | — |
| Package Type | FCBGA (Fine-pitch Chip-Scale BGA) | — |
| Process Technology | 0.15 µm CMOS | — |
| Core Supply Voltage (VCCINT) | 1.5 V | — |
| Maximum Supply Voltage | 1.575 V | — |
| Embedded Memory (RAM bits) | 655,360 (655 Kbit) | — |
| Number of LABs/ESBs | 540 | — |
| Macrocells | 16 (PLA-type grouping) | — |
| Propagation Delay (tpd) | 1.7 - 1.78 ns | — |
| Maximum Internal Clock Frequency | 376 MHz | — |
| Configuration Mode | PS / AS / JTAG | — |
| Operating Temperature Grade | Industrial (-40C to +85C) | — |
| 실장 유형 | Surface Mount (BGA) | Surface Mount (BGA) |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lifecycle | Obsolete / NRND (Altera APEX II family) | — |
| Family | — | APEX II |
| Logic Elements | — | 40,000 |
| Embedded Memory Bits | — | 655,360 bits |
| LAB/IO Rows | — | 540 |
| Effective Logic Capacity | — | 38400 LE |
| Device Type | — | FPGA (SRAM-based) |
| Core Voltage | — | 1.5 V |
| 패키지 | — | 724-ball FineLine BGA (FBGA) |
| I/O Standards | — | LVTTL, LVCMOS, LVDS, PCI, HSTL, LVPECL |
| Configuration | — | SRAM-based, JTAG, in-system programmable |
| PLL Count | — | [DATA_NEEDED: PLL count] |
| Embedded Multipliers | — | [DATA_NEEDED: multiplier count] |
| 동작 온도 | — | 0C to +85C (commercial) |
| MSL 레벨 | — | [DATA_NEEDED: MSL level] |