EP610DC-10 vs EP610IPC-10 비교
다음의 상세 나란히 비교: EP610DC-10 제조: Intel 및 EP610IPC-10 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP610DC-10 | EP610IPC-10 |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $7.95 | $16.40 |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | 16 |
| Maximum Pipelined Data Rate | 100 MHz | — |
| Pin-to-Pin Propagation Delay (tpd) | 10 ns | — |
| Speed Grade | -10 | — |
| 패키지 | 24-pin CDIP (Ceramic DIP, windowed) | 24-pin PDIP (Plastic DIP) |
| 실장 유형 | Through-Hole | — |
| Technology | CMOS, EPROM-based (UV-erasable) | CMOS EPROM (UV-erasable / OTP) |
| 공급 전압 | 5 V (single supply) | 5 V |
| 동작 온도 | 0C to +70C (commercial) | -40C to +85C (industrial) |
| I/O Pins | [DATA_NEEDED: exact I/O count for CDIP-24 variant] | 16 |
| Logic Elements | 16 macrocells (programmable AND/OR array) | — |
| Configuration Memory | UV-erasable EPROM | — |
| Reprogrammable | Yes (UV erase window on package) | — |
| RoHS 상태 | [DATA_NEEDED: not stated in verified web data] | — |
| Family | — | Altera Classic EPLD |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Programmable Gates | — | 300 usable gates |
| Maximum Operating Frequency | — | 100 MHz |
| Propagation Delay (tPD) | — | 15 ns (commerical -10 grade) |
| Product Terms | — | 160 total |
| Dedicated Inputs | — | 4 |
| Total Input Pins | — | 20 |
| Architecture | — | Turbo-only AND-OR-NOT, PAL-type |
| Programming Method | — | Altera programming hardware (UV erase for I grade, OTP for C grade) |
| TTL Emulation | — | 100% TTL compatible |