EP610PC-15 vs EP610PC-30 비교

다음의 상세 나란히 비교: EP610PC-15 제조: Altera 및 EP610PC-30 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EP610PC-15 EP610PC-30
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 NRND NRND
재고 상태 In Stock In Stock
단가 (USD) $17.50 $27.74
Family Classic EPLD —
Device Type EPLD (Erasable Programmable Logic Device) —
Usable Gates 300 gates 300
Macrocells 16 16
Logic Delay (tPD) 15 ns (pin-to-pin, -15 speed grade) —
Maximum Counter Frequency 100 MHz (per family datasheet) —
Pipelined Data Rate Up to 100 MHz —
Supply Voltage (VCC) 5 V (single supply) 5 V (4.75 V to 5.25 V)
Technology CMOS —
Architecture PAL-type, sum-of-products AND/OR array —
TTL Emulation 100% TTL compatible —
패키지 PDIP-24 (plastic DIP, 24-pin) 24-pin PDIP (0.300 inch)
핀 수 24 pins —
동작 온도 [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
실장 유형 Through-Hole (DIP) Through-Hole
RoHS 상태 [DATA_NEEDED: RoHS status] Not applicable (legacy non-compliant package per distributor listing)
Development Tool Altera MAX+PLUS II —
Logic Test Circuitry On-board for AC/DC verification —
Device Family — Classic EPLD (EP610)
Propagation Delay (tPD) — 30 ns
Maximum Pipeline Frequency — 33.3 MHz (typical) / 100 MHz pipelined
Process Technology — CMOS EPROM
Programmability — One-Time Programmable (OTP, no window on plastic PDIP)
Output Drive Current — [DATA_NEEDED: IOH/IOL per datasheet DC characteristics]
Input Pins (Dedicated) — [DATA_NEEDED: dedicated input count from datasheet pinout]
I/O Pins — [DATA_NEEDED: bidirectional I/O count from datasheet pinout]
Programming Tool — Altera A+PLUS / MAX+PLUS II (legacy)
Lead Free Status — Not applicable
Current Distributor — Rochester Electronics, LLC (authorized continuing source)

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