EP610PC-25 vs EP610PC-30 비교
다음의 상세 나란히 비교: EP610PC-25 제조: Altera 및 EP610PC-30 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP610PC-25 | EP610PC-30 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.75 | $27.74 |
| Device Family | Classic EPLD (EP610 series) | Classic EPLD (EP610) |
| Macro Cells | 16 | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tpd) | 25 ns | — |
| Maximum Pipelined Data Rate | 100 MHz | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Technology | CMOS, EPROM (UV-erasable) | — |
| Device Type | OT PLD, PAL-type, CMOS | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 20 (bidirectional, JTAG-programmable OE per macrocell) | [DATA_NEEDED: bidirectional I/O count from datasheet pinout] |
| 패키지 | PDIP-24 (0.3 inch, through-hole) | 24-pin PDIP (0.300 inch) |
| 동작 온도 | [DATA_NEEDED: operating temperature grade] | 0C to +70C (commercial) |
| Programming Method | EPROM (UV-erasable), via Altera programming hardware | — |
| 실장 유형 | Through-Hole (DIP) | Through-Hole |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | Not applicable (legacy non-compliant package per distributor listing) |
| Macrocells | — | 16 |
| Propagation Delay (tPD) | — | 30 ns |
| Maximum Pipeline Frequency | — | 33.3 MHz (typical) / 100 MHz pipelined |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Process Technology | — | CMOS EPROM |
| Programmability | — | One-Time Programmable (OTP, no window on plastic PDIP) |
| Output Drive Current | — | [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] |
| Input Pins (Dedicated) | — | [DATA_NEEDED: dedicated input count from datasheet pinout] |
| Programming Tool | — | Altera A+PLUS / MAX+PLUS II (legacy) |
| Lead Free Status | — | Not applicable |
| Current Distributor | — | Rochester Electronics, LLC (authorized continuing source) |