EP910DC-35 vs EP910DM883B 비교
다음의 상세 나란히 비교: EP910DC-35 제조: Altera 및 EP910DM883B 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP910DC-35 | EP910DM883B |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $10.95 | $7.10 |
| Device Type | UV-Erasable CMOS PLD (PAL-type) | Erasable Programmable Logic Device (EPLD) |
| Family | Classic EPLD EP910 | Classic EPLD - EP910 Series |
| Architecture | PAL-type sum-of-products AND-OR array | PAL-type AND-OR-NOT, CMOS |
| Usable Gates | 900 gates | — |
| Macrocells | 24 | 24 |
| Product Terms | 240 | 240 |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Total Inputs | 36 | — |
| Propagation Delay (tpd) | 35 ns | — |
| 최대 클록 주파수 | 37 MHz (typical, internal) | 25 MHz |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V nominal) | — |
| 동작 온도 | 0 °C to +70 °C (commercial) | -55 °C to +125 °C (military) |
| 패키지 | 40-pin CDIP (Ceramic DIP) with quartz window | CDIP-40 (Ceramic DIP, 40-pin) |
| Lead Pitch | 2.540 mm | — |
| Termination Style | Through-Hole | — |
| Programming Method | JEDEC fuse map via device programmer; UV erase | — |
| Technology | CMOS, UV-erasable EPROM cell | — |
| RoHS 상태 | Non-compliant (ceramic DIP with Pb-bearing lead finish) | [DATA_NEEDED: RoHS status] |
| Lifecycle | Obsolete / last-time-buy from authorized distributors | — |
| Manufacturer | — | Altera (now part of Intel) |
| Inputs | — | 36 |
| Outputs | — | 24 |
| Propagation Delay (tPD) | — | 40 ns (typical) |
| Supply Voltage (VCC) | — | 5 V |
| Programming Voltage (VPP) | — | 12.5 V (UV-erase window) |
| 실장 유형 | — | Through-Hole (DIP) |
| MIL Processing | — | MIL-STD-883B Class B |
| Configuration Memory | — | UV-erasable EPROM |
| Logic Elements | — | Combinational + Registered |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |